Loading...
/* SPDX-License-Identifier: GPL-2.0-or-later * * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH * Author: Teresa Remmet <t.remmet@phytec.de> */ #ifndef __PHYCORE_IMX8MM_H #define __PHYCORE_IMX8MM_H #include <linux/sizes.h> #include <linux/stringify.h> #include <asm/arch/imx-regs.h> #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_XPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif #define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc2,115200\0" \ "fdt_addr=0x48000000\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "ip_dyn=yes\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "mmcroot=2\0" \ "update_offset=0x42\0" \ "update_filename=flash.bin\0" \ "update_bootimg=" \ "mmc dev ${mmcdev} ; " \ "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \ "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ "fi\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console} " \ "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if run loadfdt; then " \ "booti ${loadaddr} - ${fdt_addr}; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi;\0 " \ "nfsroot=/nfs\0" \ "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \ "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ "run netargs; " \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ "else " \ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${loadaddr} ${image}; " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ "booti ${loadaddr} - ${fdt_addr}; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi;\0" \ /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x40000000 #define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ #endif /* __PHYCORE_IMX8MM_H */ |