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Defined in 13 files as a label:
- arch/arm/dts/socfpga.dtsi, line 636 (as a label)
- arch/arm/dts/socfpga_arria10.dtsi, line 530 (as a label)
- arch/riscv/dts/cv18xx.dtsi, line 119 (as a label)
- arch/riscv/dts/th1520.dtsi, line 202 (as a label)
- dts/upstream/src/arm/intel/socfpga/socfpga.dtsi, line 658 (as a label)
- dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi, line 536 (as a label)
- dts/upstream/src/arm/synaptics/berlin2.dtsi, line 226 (as a label)
- dts/upstream/src/arm/synaptics/berlin2cd.dtsi, line 216 (as a label)
- dts/upstream/src/arm/synaptics/berlin2q.dtsi, line 287 (as a label)
- dts/upstream/src/arm64/bitmain/bm1880-sophon-edge.dts, line 130 (as a label)
- dts/upstream/src/arm64/bitmain/bm1880.dtsi, line 162 (as a label)
- dts/upstream/src/arm64/synaptics/berlin4ct.dtsi, line 177 (as a label)
- dts/upstream/src/riscv/sophgo/cv18xx.dtsi, line 106 (as a label)
Referenced in 21 files:
- arch/arm/dts/socfpga_arria10-u-boot.dtsi, line 128
- arch/arm/dts/socfpga_arria5_secu1.dts
- arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi, line 52
- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts, line 55
- arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi, line 42
- arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts, line 84
- arch/arm/dts/socfpga_cyclone5_de10_nano.dts, line 66
- arch/arm/dts/socfpga_cyclone5_de10_standard.dts, line 66
- arch/arm/dts/socfpga_cyclone5_de1_soc.dts, line 64
- arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi, line 32
- arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi, line 68
- arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi, line 52
- arch/arm/dts/socfpga_cyclone5_sockit.dts
- arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi, line 56
- arch/arm/dts/socfpga_cyclone5_sr1500.dts, line 58
- arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi, line 52
- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
- dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dts, line 84
- dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sockit.dts
- dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_vining_fpga.dts
- dts/upstream/src/arm/synaptics/berlin2q-marvell-dmp.dts, line 91