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// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018-2021 Marvell International Ltd.
 */

#include "cn9130-db.dtsi"

/ {
	model = "Marvell CN9130 development board (CP NOR) setup(A)";

	aliases {
		spi0 = &cp0_spi1;
	};
};

/*
 * CP related configuration
 */
&cp0_pinctl {
	/* MPP Bus:
	 *	[0-11]	RGMII1
	 *	[12]	GPIO GE-IN
	 *	[13-16]	SPI1
	 *	[17-27]	NAND
	 *	[28]	MSS_GPIO[5] XXX:(mode nr from a3900)
	 *	[29-30]	SATA
	 *	[31]	MSS_GPIO[4] XXX:(mode nr from a3900)
	 *	[32,34]	SMI
	 *	[33]	SDIO
	 *	[35-36]	I2C1
	 *	[37-38]	I2C0
	 *	[39-43]	SDIOctrl
	 *	[44-55]	RGMII2
	 *	[56-62]	SDIO
	 */

		/*   0   1   2   3   4   5   6   7   8   9 */
	pin-func = < 3   3   3   3   3   3   3   3   3   3
		     3   3   0   3   3   3   3   1   1   1
		     1   1   1   1   1   1   1   1   3   9
		     9   3   7   6   7   2   2   2   2   1
		     1   1   1   1   1   1   1   1   1   1
		     1   1   1   1   1   1   0xe 0xe 0xe 0xe
		     0xe 0xe 0xe>;
};

/* U54 */
&cp0_nand {
	status = "disabled";
};

/* U55 */
&cp0_spi1 {
	status = "okay";
};