U-Boot

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2025 NXP
 */

/ {
	binman {
		multiple-images;

		m33-oei-ddrfw {
			pad-byte = <0x00>;
			align-size = <0x8>;
			filename = "m33-oei-ddrfw.bin";

			oei-m33-ddr {
				align-size = <0x4>;
				filename = "oei-m33-ddr.bin";
				type = "blob-ext";
			};

			imx-lpddr {
				type = "nxp-header-ddrfw";

				imx-lpddr-imem {
					filename = "lpddr5_imem_v202409.bin";
					type = "blob-ext";
				};

				imx-lpddr-dmem {
					filename = "lpddr5_dmem_v202409.bin";
					type = "blob-ext";
				};
			};

			imx-lpddr-qb {
				type = "nxp-header-ddrfw";

				imx-lpddr-imem-qb {
					filename = "lpddr5_imem_qb_v202409.bin";
					type = "blob-ext";
				};

				imx-lpddr-dmem-qb {
					filename = "lpddr5_dmem_qb_v202409.bin";
					type = "blob-ext";
				};
			};
		};

		imx-boot {
			filename = "flash.bin";
			pad-byte = <0x00>;

			spl {
				type = "nxp-imx9image";
				cfg-path = "spl/u-boot-spl.cfgout";
				args;

#ifndef CONFIG_IMX95_A0
				cntr-version = <2>;
#endif
				boot-from = "sd";
				soc-type = "IMX9";
#ifdef CONFIG_IMX95_A0
				append = "mx95a0-ahab-container.img";
#else
				append = "mx95b0-ahab-container.img";
#endif
				container;
#ifndef CONFIG_IMX95_A0
				dummy-ddr;
#endif
				image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
				hold = <0x10000>;
#ifdef CONFIG_IMX95_A0
				image1 = "oei", "oei-m33-tcm.bin", "0x1ffc0000";
#endif
				image2 = "m33", "m33_image.bin", "0x1ffc0000";
				image3 = "a55", "spl/u-boot-spl.bin", "0x20480000";
				dummy-v2x = <0x8b000000>;
			};

			u-boot {
				type = "nxp-imx9image";
				cfg-path = "u-boot-container.cfgout";
				args;

#ifndef CONFIG_IMX95_A0
				cntr-version = <2>;
#endif
				boot-from = "sd";
				soc-type = "IMX9";
				container;
				image0 = "a55", "bl31.bin", "0x8a200000";
				image1 = "a55", "u-boot.bin", "0x90200000";
			};
		};
	};
};

&A55_0 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_1 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_2 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_3 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_4 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&A55_5 {
	clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
	/delete-property/ power-domains;
};

&aips1 {
	bootph-all;
};

&aips2 {
	bootph-all;
};

&aips3 {
	bootph-pre-ram;
};

&clk_ext1 {
	bootph-all;
};

&elemu1 {
	bootph-all;
	status = "okay";
};

&elemu3 {
	bootph-all;
	status = "okay";
};

&{/firmware} {
	bootph-all;
};

&{/firmware/scmi} {
	bootph-all;
};

&{/firmware/scmi/protocol@11} {
	bootph-all;
};

&{/firmware/scmi/protocol@13} {
	bootph-all;
};

&{/firmware/scmi/protocol@14} {
	bootph-all;
};

&{/firmware/scmi/protocol@19} {
	bootph-all;
};

&gpio2 {
	bootph-pre-ram;
};

&gpio3 {
	bootph-pre-ram;
};

&gpio4 {
	bootph-pre-ram;
};

&gpio5 {
	bootph-pre-ram;
};

&mu2 {
	bootph-all;
};

&osc_24m {
	bootph-all;
};

&pcie0 {
	assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
					 <&scmi_clk IMX95_CLK_HSIOPLL>,
					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
	assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
				 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
};

&pcie1 {
	assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
					 <&scmi_clk IMX95_CLK_HSIOPLL>,
					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
	assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
				 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
};

&{/soc} {
	bootph-all;
};

&sram0 {
	bootph-all;
};

&scmi_buf0 {
	reg = <0x0 0x400>;
	bootph-all;
};

&scmi_buf1 {
	bootph-all;
};