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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * Copyright (C) 2020 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> */ #include "armv7-m.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/imxrt1020-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/memory/imxrt-sdram.h> / { #address-cells = <1>; #size-cells = <1>; aliases { gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; mmc0 = &usdhc1; serial0 = &lpuart1; }; clocks { ckil { compatible = "fsl,imx-ckil", "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; osc: osc { compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; }; soc { semc: semc@402f0000 { compatible = "fsl,imxrt-semc"; reg = <0x402f0000 0x4000>; clocks = <&clks IMXRT1020_CLK_SEMC>; pinctrl-0 = <&pinctrl_semc>; pinctrl-names = "default"; status = "okay"; }; lpuart1: serial@40184000 { compatible = "fsl,imxrt-lpuart"; reg = <0x40184000 0x4000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMXRT1020_CLK_LPUART1>; clock-names = "per"; status = "disabled"; }; iomuxc: iomuxc@401f8000 { compatible = "fsl,imxrt-iomuxc"; reg = <0x401f8000 0x4000>; }; anatop: anatop@400d8000 { compatible = "fsl,imxrt-anatop"; reg = <0x400d8000 0x4000>; }; clks: ccm@400fc000 { compatible = "fsl,imxrt1020-ccm"; reg = <0x400fc000 0x4000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; }; usdhc1: usdhc@402c0000 { compatible = "fsl,imxrt-usdhc"; reg = <0x402c0000 0x10000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMXRT1020_CLK_USDHC1>; clock-names = "per"; bus-width = <4>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; status = "disabled"; }; gpio1: gpio@401b8000 { compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401b8000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@401bc000 { compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401bc000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@401c0000 { compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401c0000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio5: gpio@400c0000 { compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x400c0000 0x4000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpt1: gpt1@401ec000 { compatible = "fsl,imxrt-gpt"; reg = <0x401ec000 0x4000>; interrupts = <100>; clocks = <&osc>; status = "disabled"; }; }; }; |