Open Menu / arch / arm / dts / mt7981-sd-rfb.dts
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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2022 MediaTek Inc.
 * Author: Sam Shih <sam.shih@mediatek.com>
 */

/dts-v1/;
#include "mt7981.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "mt7981-rfb";
	compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb";
	chosen {
		stdout-path = &uart0;
		tick-timer = &timer0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x10000000>;
	};

	reg_3p3v: regulator-3p3v {
		  compatible = "regulator-fixed";
		  regulator-name = "fixed-3.3V";
		  regulator-min-microvolt = <3300000>;
		  regulator-max-microvolt = <3300000>;
		  regulator-boot-on;
		  regulator-always-on;
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "disabled";
};

&eth {
	status = "okay";
	mediatek,gmac-id = <0>;
	phy-mode = "2500base-x";
	mediatek,switch = "auto";
	reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;

	fixed-link {
		speed = <2500>;
		full-duplex;
	};
};

&pio {
	spic_pins: spi1-pins-func-1 {
		mux {
			function = "spi";
			groups = "spi1_1";
		};
	};

	uart1_pins: spi1-pins-func-3 {
		mux {
			function = "uart";
			groups = "uart1_2";
		};
	};

	/* pin15 as pwm0 */
	one_pwm_pins: one-pwm-pins {
		mux {
			function = "pwm";
			groups = "pwm0_1";
		};
	};

	/* pin15 as pwm0 and pin14 as pwm1 */
	two_pwm_pins: two-pwm-pins {
		mux {
			function = "pwm";
			groups = "pwm0_1", "pwm1_0";
		};
	};

	/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
	three_pwm_pins: three-pwm-pins {
		mux {
			function = "pwm";
			groups = "pwm0_1", "pwm1_0", "pwm2";
		};
	};

	/* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
	three_pwm_pins_1: three-pwm-pins {
		mux {
			function = "pwm";
			groups = "pwm0_0", "pwm1_1", "pwm2";
		};
	};

	mmc0_pins_default: mmc0default {
		mux {
			function = "flash";
			groups =  "emmc_45";
		};
		conf-cmd-dat {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
				"SPI0_CS",  "SPI0_HOLD", "SPI0_WP",
				"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};
		conf-clk {
			pins = "SPI1_CS";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};
		conf-rst {
			pins = "PWM0";
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};
	};
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&two_pwm_pins>;
	status = "okay";
};

&watchdog {
	status = "disabled";
};

&mmc0 {
	assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
				 <&topckgen CLK_TOP_CB_NET2_D2>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins_default>;
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-sd-highspeed;
	r_smpl = <0>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	status = "okay";
};