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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2022 MediaTek Inc. * Author: Sam Shih <sam.shih@mediatek.com> */ /dts-v1/; #include "mt7988.dtsi" #include <dt-bindings/gpio/gpio.h> / { model = "mt7988-rfb"; compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb"; chosen { stdout-path = &uart0; }; memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x10000000>; }; reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; &uart0 { status = "okay"; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "okay"; }; ð0 { status = "okay"; phy-mode = "usxgmii"; mediatek,switch = "mt7988"; fixed-link { speed = <10000>; full-duplex; pause; }; }; &pio { i2c1_pins: i2c1-pins { mux { function = "i2c"; groups = "i2c1_0"; }; }; pwm_pins: pwm-pins { mux { function = "pwm"; groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7"; }; }; spi0_pins: spi0-pins { mux { function = "spi"; groups = "spi0", "spi0_wp_hold"; }; }; mmc1_pins_default: mmc1default { mux { function = "flash"; groups = "emmc_45"; }; conf-cmd-dat { pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI", "SPI2_CLK", "SPI2_HOLD"; input-enable; drive-strength = <MTK_DRIVE_4mA>; }; conf-clk { pins = "SPI2_WP"; drive-strength = <MTK_DRIVE_4mA>; }; }; }; &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm_pins>; status = "okay"; }; &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; #address-cells = <1>; #size-cells = <0>; status = "okay"; enhance_timing; dma_ext; ipm_design; support_quad; tick_dly = <2>; sample_sel = <0>; spi_nand@0 { compatible = "spi-nand"; reg = <0>; spi-max-frequency = <52000000>; }; }; &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_default>; max-frequency = <52000000>; bus-width = <4>; cap-sd-highspeed; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_3p3v>; status = "okay"; }; |