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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 | /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> * * (C) Copyright 2009 Freescale Semiconductor, Inc. */ #include <config.h> #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> #include <linux/linkage.h> .section ".text.init", "x" .macro init_arm_erratum /* ARM erratum ID #468414 */ mrc 15, 0, r1, c1, c0, 1 orr r1, r1, #(1 << 5) /* enable L1NEON bit */ mcr 15, 0, r1, c1, c0, 1 .endm /* * L2CC Cache setup/invalidation/disable */ .macro init_l2cc /* explicitly disable L2 cache */ mrc 15, 0, r0, c1, c0, 1 bic r0, r0, #0x2 mcr 15, 0, r0, c1, c0, 1 /* reconfigure L2 cache aux control reg */ ldr r0, =0xC0 | /* tag RAM */ \ 0x4 | /* data RAM */ \ 1 << 24 | /* disable write allocate delay */ \ 1 << 23 | /* disable write allocate combine */ \ 1 << 22 /* disable write allocate */ #if defined(CONFIG_MX51) ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ orrls r0, r0, #1 << 25 #endif mcr 15, 1, r0, c9, c0, 2 /* enable L2 cache */ mrc 15, 0, r0, c1, c0, 1 orr r0, r0, #2 mcr 15, 0, r0, c1, c0, 1 .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. * The PACR default values are good.*/ .macro init_aips /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ ldr r0, =AIPS1_BASE_ADDR ldr r1, =0x77777777 str r1, [r0, #0x0] str r1, [r0, #0x4] ldr r0, =AIPS2_BASE_ADDR str r1, [r0, #0x0] str r1, [r0, #0x4] /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ .endm /* init_aips */ /* M4IF setup */ .macro init_m4if #ifdef CONFIG_MX51 /* VPU and IPU given higher priority (0x4) * IPU accesses with ID=0x1 given highest priority (=0xA) */ ldr r0, =M4IF_BASE_ADDR ldr r1, =0x00000203 str r1, [r0, #0x40] str r4, [r0, #0x44] ldr r1, =0x00120125 str r1, [r0, #0x9C] ldr r1, =0x001901A3 str r1, [r0, #0x48] #endif .endm /* init_m4if */ .macro setup_pll pll, freq ldr r0, =\pll adr r2, W_DP_\freq bl setup_pll_func .endm #define W_DP_OP 0 #define W_DP_MFD 4 #define W_DP_MFN 8 setup_pll_func: ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ mov r1, #0x2 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ ldr r1, [r2, #W_DP_OP] str r1, [r0, #PLL_DP_OP] str r1, [r0, #PLL_DP_HFS_OP] ldr r1, [r2, #W_DP_MFD] str r1, [r0, #PLL_DP_MFD] str r1, [r0, #PLL_DP_HFS_MFD] ldr r1, [r2, #W_DP_MFN] str r1, [r0, #PLL_DP_MFN] str r1, [r0, #PLL_DP_HFS_MFN] ldr r1, =0x00001232 str r1, [r0, #PLL_DP_CTL] 1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 beq 1b /* r10 saved upper lr */ mov pc, lr .macro setup_pll_errata pll, freq ldr r2, =\pll str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */ ldr r1, =0x00001236 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */ 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */ ands r1, r1, #0x1 beq 1b ldr r5, \freq str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */ str r5, [r2, #PLL_DP_HFS_MFN] mov r1, #0x1 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */ 2: ldr r1, [r2, #PLL_DP_CONFIG] tst r1, #1 bne 2b ldr r1, =100 /* Wait at least 4 us */ 3: subs r1, r1, #1 bge 3b mov r1, #0x2 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ .endm .macro init_clock #if defined (CONFIG_MX51) ldr r0, =CCM_BASE_ADDR /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] str r4, [r0, #CLKCTL_CCGR1] str r4, [r0, #CLKCTL_CCGR2] str r4, [r0, #CLKCTL_CCGR3] ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4] ldr r1, =0x00FFF030 str r1, [r0, #CLKCTL_CCGR5] ldr r1, =0x00000300 str r1, [r0, #CLKCTL_CCGR6] /* Disable IPU and HSC dividers */ mov r1, #0x60000 str r1, [r0, #CLKCTL_CCDR] /* Make sure to switch the DDR away from PLL 1 */ ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] /* make sure divider effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b /* Switch ARM to step clock */ mov r1, #0x4 str r1, [r0, #CLKCTL_CCSR] #if defined(CONFIG_MX51_PLL_ERRATA) setup_pll PLL1_BASE_ADDR, 864 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT #else setup_pll PLL1_BASE_ADDR, 800 #endif setup_pll PLL3_BASE_ADDR, 665 /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] setup_pll PLL2_BASE_ADDR, 665 /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] setup_pll PLL3_BASE_ADDR, 216 /* Set the platform clock dividers */ ldr r0, =ARM_BASE_ADDR ldr r1, =0x00000725 str r1, [r0, #0x14] ldr r0, =CCM_BASE_ADDR /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0 str r1, [r0, #CLKCTL_CACRR] /* Switch ARM back to PLL 1 */ str r4, [r0, #CLKCTL_CCSR] /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CFG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] /* Restore the default values in the Gate registers */ ldr r1, =0xFFFFFFFF str r1, [r0, #CLKCTL_CCGR0] str r1, [r0, #CLKCTL_CCGR1] str r1, [r0, #CLKCTL_CCGR2] str r1, [r0, #CLKCTL_CCGR3] str r1, [r0, #CLKCTL_CCGR4] str r1, [r0, #CLKCTL_CCGR5] str r1, [r0, #CLKCTL_CCGR6] /* Use PLL 2 for UART's, get 66.5MHz from it */ ldr r1, =0xA5A2A020 str r1, [r0, #CLKCTL_CSCMR1] ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] /* make sure divider effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b str r4, [r0, #CLKCTL_CCDR] /* for cko - for ARM div by 8 */ mov r1, #0x000A0000 add r1, r1, #0x00000F0 str r1, [r0, #CLKCTL_CCOSR] #else /* CONFIG_MX53 */ ldr r0, =CCM_BASE_ADDR /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] str r4, [r0, #CLKCTL_CCGR1] str r4, [r0, #CLKCTL_CCGR2] str r4, [r0, #CLKCTL_CCGR3] str r4, [r0, #CLKCTL_CCGR7] ldr r1, =0x00030000 str r1, [r0, #CLKCTL_CCGR4] ldr r1, =0x00FFF030 str r1, [r0, #CLKCTL_CCGR5] ldr r1, =0x0F00030F str r1, [r0, #CLKCTL_CCGR6] /* Switch ARM to step clock */ mov r1, #0x4 str r1, [r0, #CLKCTL_CCSR] setup_pll PLL1_BASE_ADDR, 800 setup_pll PLL3_BASE_ADDR, 400 /* Switch peripheral to PLL3 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00015154 str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x02898945 str r1, [r0, #CLKCTL_CBCDR] /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b setup_pll PLL2_BASE_ADDR, 400 /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00888945 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x00016154 str r1, [r0, #CLKCTL_CBCMR] /*change uart clk parent to pll2*/ ldr r1, [r0, #CLKCTL_CSCMR1] and r1, r1, #0xfcffffff orr r1, r1, #0x01000000 str r1, [r0, #CLKCTL_CSCMR1] /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b setup_pll PLL3_BASE_ADDR, 216 setup_pll PLL4_BASE_ADDR, 455 /* Set the platform clock dividers */ ldr r0, =ARM_BASE_ADDR ldr r1, =0x00000124 str r1, [r0, #0x14] ldr r0, =CCM_BASE_ADDR mov r1, #0 str r1, [r0, #CLKCTL_CACRR] /* Switch ARM back to PLL 1. */ mov r1, #0x0 str r1, [r0, #CLKCTL_CCSR] /* make uart div=6 */ ldr r1, [r0, #CLKCTL_CSCDR1] and r1, r1, #0xffffffc0 orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] /* Restore the default values in the Gate registers */ ldr r1, =0xFFFFFFFF str r1, [r0, #CLKCTL_CCGR0] str r1, [r0, #CLKCTL_CCGR1] str r1, [r0, #CLKCTL_CCGR2] str r1, [r0, #CLKCTL_CCGR3] str r1, [r0, #CLKCTL_CCGR4] str r1, [r0, #CLKCTL_CCGR5] str r1, [r0, #CLKCTL_CCGR6] str r1, [r0, #CLKCTL_CCGR7] mov r1, #0x00000 str r1, [r0, #CLKCTL_CCDR] /* for cko - for ARM div by 8 */ mov r1, #0x000A0000 add r1, r1, #0x00000F0 str r1, [r0, #CLKCTL_CCOSR] #endif /* CONFIG_MX53 */ .endm ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ #if defined(CFG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 str r1, [r0, #0x0] ldr r1, [r0, #0x4] orr r1, r1, #1 << 23 str r1, [r0, #0x4] #endif init_arm_erratum init_l2cc init_aips init_m4if init_clock mov pc, r10 ENDPROC(lowlevel_init) /* Board level setting value */ #if defined(CONFIG_MX51_PLL_ERRATA) W_DP_864: .word DP_OP_864 .word DP_MFD_864 .word DP_MFN_864 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT #else W_DP_800: .word DP_OP_800 .word DP_MFD_800 .word DP_MFN_800 #endif #if defined(CONFIG_MX51) W_DP_665: .word DP_OP_665 .word DP_MFD_665 .word DP_MFN_665 #endif W_DP_216: .word DP_OP_216 .word DP_MFD_216 .word DP_MFN_216 W_DP_400: .word DP_OP_400 .word DP_MFD_400 .word DP_MFN_400 W_DP_455: .word DP_OP_455 .word DP_MFD_455 .word DP_MFN_455 |