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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 | // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2007 * Sascha Hauer, Pengutronix * * (C) Copyright 2009 Freescale Semiconductor, Inc. */ #include <cpu_func.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/cache.h> #include <linux/errno.h> #include <asm/io.h> #include <asm/mach-imx/boot_mode.h> #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) #error "CPU_TYPE not defined" #endif u32 get_cpu_rev(void) { #ifdef CONFIG_MX51 int system_rev = 0x51000; #else int system_rev = 0x53000; #endif int reg = __raw_readl(ROM_SI_REV); #if defined(CONFIG_MX51) switch (reg) { case 0x02: system_rev |= CHIP_REV_1_1; break; case 0x10: if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) system_rev |= CHIP_REV_2_5; else system_rev |= CHIP_REV_2_0; break; case 0x20: system_rev |= CHIP_REV_3_0; break; default: system_rev |= CHIP_REV_1_0; break; } #else if (reg < 0x20) system_rev |= CHIP_REV_1_0; else system_rev |= reg; #endif return system_rev; } #ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { return get_cpu_rev(); } #endif #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } #endif #if defined(CONFIG_FEC_MXC) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { int i; struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; struct fuse_bank *bank = &iim->bank[1]; struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs; for (i = 0; i < 6; i++) mac[i] = readl(&fuse->mac_addr[i]) & 0xff; } #endif #ifdef CONFIG_MX53 #define IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT BIT(30) void boot_mode_apply(unsigned cfg_val) { void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr; if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT) clrbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT); else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT) setbits_le32(lpgr, IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT); else writel(cfg_val, lpgr); } int boot_mode_getprisec(void) { void *lpgr = &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr; return !!(readl(lpgr) & IMX53_SRTC_LPGR_PERSIST_SECONDARY_BOOT); } /* * cfg_val will be used for * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] * * If bit 28 of LPGR is set upon watchdog reset, * bits[25:0] of LPGR will move to SBMR. */ const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, /* usb or serial download */ {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)}, {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)}, {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)}, {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)}, {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)}, {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)}, /* 4 bit bus width */ {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)}, {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)}, {"primary", MAKE_CFGVAL_PRIMARY_BOOT}, {"secondary", MAKE_CFGVAL_SECONDARY_BOOT}, {NULL, 0}, }; #endif |