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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. * Copyright (C) 2016 Grinn */ #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/iomux.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/mx6ul_pins.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> #include <asm/io.h> #include <config.h> #include <fsl_esdhc_imx.h> #include <linux/delay.h> #include <linux/sizes.h> #include <mmc.h> DECLARE_GLOBAL_DATA_PTR; #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) int dram_init(void) { gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const emmc_pads[] = { MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* RST_B */ MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), }; #ifdef CONFIG_FSL_ESDHC_IMX static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8}; #define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10) int litesom_mmc_init(struct bd_info *bis) { int ret; /* eMMC */ imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads)); gpio_direction_output(EMMC_PWR_GPIO, 0); udelay(500); gpio_direction_output(EMMC_PWR_GPIO, 1); emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); ret = fsl_esdhc_initialize(bis, &emmc_cfg); if (ret) { printf("Warning: failed to initialize mmc dev 1 (eMMC)\n"); return ret; } return 0; } #endif #ifdef CONFIG_XPL_BUILD #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { .grp_addds = 0x00000030, .grp_ddrmode_ctl = 0x00020000, .grp_b0ds = 0x00000030, .grp_ctlds = 0x00000030, .grp_b1ds = 0x00000030, .grp_ddrpke = 0x00000000, .grp_ddrmode = 0x00020000, .grp_ddr_type = 0x000c0000, }; static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { .dram_dqm0 = 0x00000030, .dram_dqm1 = 0x00000030, .dram_ras = 0x00000030, .dram_cas = 0x00000030, .dram_odt0 = 0x00000030, .dram_odt1 = 0x00000030, .dram_sdba2 = 0x00000000, .dram_sdclk_0 = 0x00000030, .dram_sdqs0 = 0x00000030, .dram_sdqs1 = 0x00000030, .dram_reset = 0x00000030, }; static struct mx6_mmdc_calibration mx6_mmcd_calib = { .p0_mpwldectrl0 = 0x00000000, .p0_mpdgctrl0 = 0x41570155, .p0_mprddlctl = 0x4040474A, .p0_mpwrdlctl = 0x40405550, }; struct mx6_ddr_sysinfo ddr_sysinfo = { .dsize = 0, .cs_density = 20, .ncs = 1, .cs1_mirror = 0, .rtt_wr = 2, .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ .walat = 0, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, .refsel = 0, /* Refresh cycles at 64KHz */ .refr = 1, /* 2 refresh commands per refresh cycle */ }; static struct mx6_ddr3_cfg mem_ddr = { .mem_speed = 800, .density = 4, .width = 16, .banks = 8, .rowaddr = 15, .coladdr = 10, .pagesz = 2, .trcd = 1375, .trcmin = 4875, .trasmin = 3500, }; static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; writel(0xFFFFFFFF, &ccm->CCGR0); writel(0xFFFFFFFF, &ccm->CCGR1); writel(0xFFFFFFFF, &ccm->CCGR2); writel(0xFFFFFFFF, &ccm->CCGR3); writel(0xFFFFFFFF, &ccm->CCGR4); writel(0xFFFFFFFF, &ccm->CCGR5); writel(0xFFFFFFFF, &ccm->CCGR6); writel(0xFFFFFFFF, &ccm->CCGR7); } static void spl_dram_init(void) { unsigned long ram_size; mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); /* * Get actual RAM size, so we can adjust DDR row size for <512M * memories */ ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); if (ram_size < SZ_512M) { mem_ddr.rowaddr = 14; mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); } } void litesom_init_f(void) { ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); #ifdef CONFIG_BOARD_EARLY_INIT_F board_early_init_f(); #endif /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); } #endif |