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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 | /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ /* * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved */ /* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */ #define CPU_STM32MP157Cxx 0x05000000 #define CPU_STM32MP157Axx 0x05000001 #define CPU_STM32MP153Cxx 0x05000024 #define CPU_STM32MP153Axx 0x05000025 #define CPU_STM32MP151Cxx 0x0500002E #define CPU_STM32MP151Axx 0x0500002F #define CPU_STM32MP157Fxx 0x05000080 #define CPU_STM32MP157Dxx 0x05000081 #define CPU_STM32MP153Fxx 0x050000A4 #define CPU_STM32MP153Dxx 0x050000A5 #define CPU_STM32MP151Fxx 0x050000AE #define CPU_STM32MP151Dxx 0x050000AF #define CPU_STM32MP135Cxx 0x05010000 #define CPU_STM32MP135Axx 0x05010001 #define CPU_STM32MP133Cxx 0x050100C0 #define CPU_STM32MP133Axx 0x050100C1 #define CPU_STM32MP131Cxx 0x050106C8 #define CPU_STM32MP131Axx 0x050106C9 #define CPU_STM32MP135Fxx 0x05010800 #define CPU_STM32MP135Dxx 0x05010801 #define CPU_STM32MP133Fxx 0x050108C0 #define CPU_STM32MP133Dxx 0x050108C1 #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9 /* ID for STM32MP21x = Device Part Number (RPN) (bit31:0) */ #define CPU_STM32MP211Axx 0x40073E7D #define CPU_STM32MP211Cxx 0x0007307D #define CPU_STM32MP211Dxx 0xC0073E7D #define CPU_STM32MP211Fxx 0x8007307D #define CPU_STM32MP213Axx 0x40073E1D #define CPU_STM32MP213Cxx 0x0007301D #define CPU_STM32MP213Dxx 0xC0073E1D #define CPU_STM32MP213Fxx 0x8007301D #define CPU_STM32MP215Axx 0x40033E0D #define CPU_STM32MP215Cxx 0x0003300D #define CPU_STM32MP215Dxx 0xC0033E0D #define CPU_STM32MP215Fxx 0x8003300D /* ID for STM32MP23x = Device Part Number (RPN) (bit31:0) */ #define CPU_STM32MP235Cxx 0x00082182 #define CPU_STM32MP233Cxx 0x000B318E #define CPU_STM32MP231Cxx 0x000B31EF #define CPU_STM32MP235Axx 0x40082F82 #define CPU_STM32MP233Axx 0x400B3F8E #define CPU_STM32MP231Axx 0x400B3FEF #define CPU_STM32MP235Fxx 0x80082182 #define CPU_STM32MP233Fxx 0x800B318E #define CPU_STM32MP231Fxx 0x800B31EF #define CPU_STM32MP235Dxx 0xC0082F82 #define CPU_STM32MP233Dxx 0xC00B3F8E #define CPU_STM32MP231Dxx 0xC00B3FEF /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ #define CPU_STM32MP257Cxx 0x00002000 #define CPU_STM32MP255Cxx 0x00082000 #define CPU_STM32MP253Cxx 0x000B2004 #define CPU_STM32MP251Cxx 0x000B3065 #define CPU_STM32MP257Axx 0x40002E00 #define CPU_STM32MP255Axx 0x40082E00 #define CPU_STM32MP253Axx 0x400B2E04 #define CPU_STM32MP251Axx 0x400B3E65 #define CPU_STM32MP257Fxx 0x80002000 #define CPU_STM32MP255Fxx 0x80082000 #define CPU_STM32MP253Fxx 0x800B2004 #define CPU_STM32MP251Fxx 0x800B3065 #define CPU_STM32MP257Dxx 0xC0002E00 #define CPU_STM32MP255Dxx 0xC0082E00 #define CPU_STM32MP253Dxx 0xC00B2E04 #define CPU_STM32MP251Dxx 0xC00B3E65 /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 #define CPU_DEV_STM32MP21 0x503 #define CPU_DEV_STM32MP23 0x505 #define CPU_DEV_STM32MP25 0x505 /* return CPU_DEV constants */ u32 get_cpu_dev(void); /* Silicon revision = REV_ID[15:0] of Device Version */ #define CPU_REV1 0x1000 #define CPU_REV1_1 0x1001 #define CPU_REV1_2 0x1003 #define CPU_REV2 0x2000 #define CPU_REV2_1 0x2001 #define CPU_REV2_2 0x2003 /* OTP revision ID = 6 bits : 3 for Major / 3 for Minor */ #define OTP_REVID_1 0b001000 #define OTP_REVID_1_1 0b001001 #define OTP_REVID_1_2 0b001010 #define OTP_REVID_2 0b010000 #define OTP_REVID_2_1 0b010001 #define OTP_REVID_2_2 0b010010 /* return SoC revision = Silicon revision (STM32MP1) or OTP revision ID (STM32MP2)*/ u32 get_cpu_rev(void); /* Get Package options from OTP */ u32 get_cpu_package(void); /* package used for STM32MP15x */ #define STM32MP15_PKG_AA_LBGA448 4 #define STM32MP15_PKG_AB_LBGA354 3 #define STM32MP15_PKG_AC_TFBGA361 2 #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0 /* package used for STM32MP21x */ #define STM32MP21_PKG_CUSTOM 0 #define STM32MP21_PKG_AL_VFBGA361 1 #define STM32MP21_PKG_AN_VFBGA273 3 #define STM32MP21_PKG_AO_VFBGA225 4 #define STM32MP21_PKG_AM_TFBGA289 5 /* package used for STM32MP23x */ #define STM32MP23_PKG_CUSTOM 0 #define STM32MP23_PKG_AL_VFBGA361 1 #define STM32MP23_PKG_AK_VFBGA424 3 #define STM32MP23_PKG_AJ_TFBGA361 7 /* package used for STM32MP25x */ #define STM32MP25_PKG_CUSTOM 0 #define STM32MP25_PKG_AL_VFBGA361 1 #define STM32MP25_PKG_AK_VFBGA424 3 #define STM32MP25_PKG_AI_TFBGA436 5 #define STM32MP25_PKG_UNKNOWN 7 /* Get SOC name */ #define SOC_NAME_SIZE 20 void get_soc_name(char name[SOC_NAME_SIZE]); /* return boot mode */ u32 get_bootmode(void); /* return auth status and partition */ u32 get_bootauth(void); int get_eth_nb(void); int setup_mac_address(void); int setup_serial_number(void); /* board power management : configure vddcore according OPP */ void board_vddcore_init(u32 voltage_mv); /* weak function */ void stm32mp_cpu_init(void); void stm32mp_misc_init(void); /* helper function: read data from OTP */ u32 get_otp(int index, int shift, int mask); uintptr_t get_stm32mp_rom_api_table(void); uintptr_t get_stm32mp_bl2_dtb(void); /* helper function: check "closed" state in product "Life Cycle" */ #ifdef CONFIG_CMD_STM32KEY bool stm32mp_is_closed(void); #else static inline bool stm32mp_is_closed(void) { return false; } #endif |