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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2018 Microsemi Corporation */ /dts-v1/; #include "mscc,jr2.dtsi" #include <dt-bindings/mscc/jr2_data.h> / { model = "Serval2 NID PCB112 Reference Board"; compatible = "mscc,serval2-pcb110", "mscc,jr2"; aliases { spi0 = &spi0; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; gpio-leds { compatible = "gpio-leds"; status_green { label = "pcb110:green:status"; gpios = <&gpio 12 0>; default-state = "on"; }; status_red { label = "pcb110:red:status"; gpios = <&gpio 13 0>; default-state = "off"; }; }; }; &uart0 { status = "okay"; }; &spi0 { status = "okay"; spi-flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <18000000>; /* input clock */ reg = <0>; /* CS0 */ }; }; &sgpio { status = "okay"; sgpio-ports = <0x0000ffff>; }; &sgpio2 { status = "okay"; sgpio-ports = <0x3fe0ffff>; }; &mdio0 { status = "okay"; phy16: ethernet-phy@16 { reg = <16>; }; phy17: ethernet-phy@17 { reg = <17>; }; phy18: ethernet-phy@18 { reg = <18>; }; phy19: ethernet-phy@19 { reg = <19>; }; }; &switch { ethernet-ports { port0: port@0 { reg = <24>; phy-handle = <&phy16>; phys = <&serdes_hsio 24 SERDES6G(0) PHY_MODE_SGMII>; }; port1: port@1 { reg = <25>; phy-handle = <&phy17>; phys = <&serdes_hsio 25 SERDES6G(1) PHY_MODE_SGMII>; }; port2: port@2 { reg = <26>; phy-handle = <&phy18>; phys = <&serdes_hsio 26 SERDES6G(2) PHY_MODE_SGMII>; }; port3: port@3 { reg = <27>; phy-handle = <&phy19>; phys = <&serdes_hsio 27 SERDES6G(3) PHY_MODE_SGMII>; }; }; }; |