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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 | // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ /* * MPC8xx Internal Memory Map Functions */ #include <command.h> #include <asm/global_data.h> #include <asm/immap_8xx.h> #include <asm/cpm_8xx.h> #include <asm/iopin_8xx.h> #include <asm/io.h> #include <asm/ppc.h> DECLARE_GLOBAL_DATA_PTR; static int do_siuinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; sysconf8xx_t __iomem *sc = &immap->im_siu_conf; printf("SIUMCR= %08x SYPCR = %08x\n", in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr)); printf("SWT = %08x\n", in_be32(&sc->sc_swt)); printf("SIPEND= %08x SIMASK= %08x\n", in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask)); printf("SIEL = %08x SIVEC = %08x\n", in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec)); printf("TESR = %08x SDCR = %08x\n", in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr)); return 0; } static int do_memcinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; memctl8xx_t __iomem *memctl = &immap->im_memctl; int nbanks = 8; uint __iomem *p = &memctl->memc_br0; int i; for (i = 0; i < nbanks; i++, p += 2) printf("BR%-2d = %08x OR%-2d = %08x\n", i, in_be32(p), i, in_be32(p + 1)); printf("MAR = %08x", in_be32(&memctl->memc_mar)); printf(" MCR = %08x\n", in_be32(&memctl->memc_mcr)); printf("MAMR = %08x MBMR = %08x", in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr)); printf("\nMSTAT = %04x\n", in_be16(&memctl->memc_mstat)); printf("MPTPR = %04x MDR = %08x\n", in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr)); return 0; } static int do_carinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; car8xx_t __iomem *car = &immap->im_clkrst; printf("SCCR = %08x\n", in_be32(&car->car_sccr)); printf("PLPRCR= %08x\n", in_be32(&car->car_plprcr)); printf("RSR = %08x\n", in_be32(&car->car_rsr)); return 0; } static int counter; static void header(void) { char *data = "\ -------------------------------- --------------------------------\ 00000000001111111111222222222233 00000000001111111111222222222233\ 01234567890123456789012345678901 01234567890123456789012345678901\ -------------------------------- --------------------------------\ "; int i; if (counter % 2) putc('\n'); counter = 0; for (i = 0; i < 4; i++, data += 79) printf("%.79s\n", data); } static void binary(char *label, uint value, int nbits) { uint mask = 1 << (nbits - 1); int i, second = (counter++ % 2); if (second) putc(' '); puts(label); for (i = 32 + 1; i != nbits; i--) putc(' '); while (mask != 0) { if (value & mask) putc('1'); else putc('0'); mask >>= 1; } if (second) putc('\n'); } #define PA_NBITS 16 #define PA_NB_ODR 8 #define PB_NBITS 18 #define PB_NB_ODR 16 #define PC_NBITS 12 #define PD_NBITS 13 static int do_iopinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; iop8xx_t __iomem *iop = &immap->im_ioport; ushort __iomem *l, *r; uint __iomem *R; counter = 0; header(); /* * Ports A & B */ l = &iop->iop_padir; R = &immap->im_cpm.cp_pbdir; binary("PA_DIR", in_be16(l++), PA_NBITS); binary("PB_DIR", in_be32(R++), PB_NBITS); binary("PA_PAR", in_be16(l++), PA_NBITS); binary("PB_PAR", in_be32(R++), PB_NBITS); binary("PA_ODR", in_be16(l++), PA_NB_ODR); binary("PB_ODR", in_be32(R++), PB_NB_ODR); binary("PA_DAT", in_be16(l++), PA_NBITS); binary("PB_DAT", in_be32(R++), PB_NBITS); header(); /* * Ports C & D */ l = &iop->iop_pcdir; r = &iop->iop_pddir; binary("PC_DIR", in_be16(l++), PC_NBITS); binary("PD_DIR", in_be16(r++), PD_NBITS); binary("PC_PAR", in_be16(l++), PC_NBITS); binary("PD_PAR", in_be16(r++), PD_NBITS); binary("PC_SO ", in_be16(l++), PC_NBITS); binary(" ", 0, 0); r++; binary("PC_DAT", in_be16(l++), PC_NBITS); binary("PD_DAT", in_be16(r++), PD_NBITS); binary("PC_INT", in_be16(l++), PC_NBITS); header(); return 0; } /* * set the io pins * this needs a clean up for smaller tighter code * use *uint and set the address based on cmd + port */ static int do_iopset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { uint rcode = 0; iopin_t iopin; static uint port; static uint pin; static uint value; static enum { DIR, PAR, SOR, ODR, DAT, INT } cmd = DAT; if (argc != 5) { puts("iopset PORT PIN CMD VALUE\n"); return 1; } port = argv[1][0] - 'A'; if (port > 3) port -= 0x20; if (port > 3) rcode = 1; pin = simple_strtol(argv[2], NULL, 10); if (pin > 31) rcode = 1; switch (argv[3][0]) { case 'd': if (argv[3][1] == 'a') cmd = DAT; else if (argv[3][1] == 'i') cmd = DIR; else rcode = 1; break; case 'p': cmd = PAR; break; case 'o': cmd = ODR; break; case 's': cmd = SOR; break; case 'i': cmd = INT; break; default: printf("iopset: unknown command %s\n", argv[3]); rcode = 1; } if (argv[4][0] == '1') value = 1; else if (argv[4][0] == '0') value = 0; else rcode = 1; if (rcode == 0) { iopin.port = port; iopin.pin = pin; iopin.flag = 0; switch (cmd) { case DIR: if (value) iopin_set_out(&iopin); else iopin_set_in(&iopin); break; case PAR: if (value) iopin_set_ded(&iopin); else iopin_set_gen(&iopin); break; case SOR: if (value) iopin_set_opt2(&iopin); else iopin_set_opt1(&iopin); break; case ODR: if (value) iopin_set_odr(&iopin); else iopin_set_act(&iopin); break; case DAT: if (value) iopin_set_high(&iopin); else iopin_set_low(&iopin); break; case INT: if (value) iopin_set_falledge(&iopin); else iopin_set_anyedge(&iopin); break; } } return rcode; } static void prbrg(int n, uint val) { uint extc = (val >> 14) & 3; uint cd = (val & CPM_BRG_CD_MASK) >> 1; uint div16 = (val & CPM_BRG_DIV16) != 0; ulong clock = gd->cpu_clk; printf("BRG%d:", n); if (val & CPM_BRG_RST) puts(" RESET"); else puts(" "); if (val & CPM_BRG_EN) puts(" ENABLED"); else puts(" DISABLED"); printf(" EXTC=%d", extc); if (val & CPM_BRG_ATB) puts(" ATB"); else puts(" "); printf(" DIVIDER=%4d", cd); if (extc == 0 && cd != 0) { uint baudrate; if (div16) baudrate = (clock / 16) / (cd + 1); else baudrate = clock / (cd + 1); printf("=%6d bps", baudrate); } else { puts(" "); } if (val & CPM_BRG_DIV16) puts(" DIV16"); else puts(" "); putc('\n'); } static int do_brginfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; cpm8xx_t __iomem *cp = &immap->im_cpm; uint __iomem *p = &cp->cp_brgc1; int i = 1; while (i <= 4) prbrg(i++, in_be32(p++)); return 0; } #ifdef CONFIG_CMD_REGINFO void print_reginfo(void) { immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; sit8xx_t __iomem *timers = &immap->im_sit; printf("\nSystem Configuration registers\n" "\tIMMR\t0x%08X\n", get_immr()); do_siuinfo(NULL, 0, 0, NULL); printf("Memory Controller Registers\n"); do_memcinfo(NULL, 0, 0, NULL); printf("\nSystem Integration Timers\n"); printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n", in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc)); printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr)); } #endif /***************************************************/ U_BOOT_CMD( siuinfo, 1, 1, do_siuinfo, "print System Interface Unit (SIU) registers", "" ); U_BOOT_CMD( memcinfo, 1, 1, do_memcinfo, "print Memory Controller registers", "" ); U_BOOT_CMD( carinfo, 1, 1, do_carinfo, "print Clocks and Reset registers", "" ); U_BOOT_CMD( iopinfo, 1, 1, do_iopinfo, "print I/O Port registers", "" ); U_BOOT_CMD( iopset, 5, 0, do_iopset, "set I/O Port registers", "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" ); U_BOOT_CMD( brginfo, 1, 1, do_brginfo, "print Baud Rate Generator (BRG) registers", "" ); |