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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; #include "binman.dtsi" #include "ae350-u-boot.dtsi" / { #address-cells = <2>; #size-cells = <2>; compatible = "andestech,ax25"; model = "andestech,ax25"; aliases { uart0 = &serial0; spi0 = &spi; }; chosen { bootargs = "console=ttyS0,38400n8 debug loglevel=7"; stdout-path = "uart0:38400n8"; }; cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <60000000>; CPU0: cpu@0 { device_type = "cpu"; reg = <0>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdc"; riscv,priv-major = <1>; riscv,priv-minor = <10>; mmu-type = "riscv,sv39"; clock-frequency = <60000000>; i-cache-size = <0x8000>; i-cache-line-size = <32>; d-cache-size = <0x8000>; d-cache-line-size = <32>; next-level-cache = <&L2>; CPU0_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; CPU1: cpu@1 { device_type = "cpu"; reg = <1>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdc"; riscv,priv-major = <1>; riscv,priv-minor = <10>; mmu-type = "riscv,sv39"; clock-frequency = <60000000>; i-cache-size = <0x8000>; i-cache-line-size = <32>; d-cache-size = <0x8000>; d-cache-line-size = <32>; next-level-cache = <&L2>; CPU1_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; CPU2: cpu@2 { device_type = "cpu"; reg = <2>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdc"; riscv,priv-major = <1>; riscv,priv-minor = <10>; mmu-type = "riscv,sv39"; clock-frequency = <60000000>; i-cache-size = <0x8000>; i-cache-line-size = <32>; d-cache-size = <0x8000>; d-cache-line-size = <32>; next-level-cache = <&L2>; CPU2_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; CPU3: cpu@3 { device_type = "cpu"; reg = <3>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdc"; riscv,priv-major = <1>; riscv,priv-minor = <10>; mmu-type = "riscv,sv39"; clock-frequency = <60000000>; i-cache-size = <0x8000>; i-cache-line-size = <32>; d-cache-size = <0x8000>; d-cache-line-size = <32>; next-level-cache = <&L2>; CPU3_intc: interrupt-controller { #interrupt-cells = <1>; interrupt-controller; compatible = "riscv,cpu-intc"; }; }; }; L2: l2-cache@e0500000 { compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0x0 0xe0500000 0x0 0x40000>; andes,inst-prefetch = <3>; andes,data-prefetch = <3>; /* The value format is <XRAMOCTL XRAMICTL> */ andes,tag-ram-ctl = <0 0>; andes,data-ram-ctl = <0 0>; }; memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x0 0x40000000>; }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges; plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; riscv,ndev=<71>; interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 &CPU2_intc 11 &CPU2_intc 9 &CPU3_intc 11 &CPU3_intc 9>; }; plicsw: interrupt-controller@e6400000 { compatible = "andestech,plicsw"; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>; riscv,ndev=<2>; interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>; }; plmt0@e6000000 { compatible = "andestech,plmt0"; interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 &CPU2_intc 7 &CPU3_intc 7>; reg = <0x0 0xe6000000 0x0 0x100000>; }; }; spiclk: virt_100mhz { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <100000000>; }; timer0: timer@f0400000 { compatible = "andestech,atcpit100"; reg = <0x0 0xf0400000 0x0 0x1000>; clock-frequency = <60000000>; interrupts = <3 4>; interrupt-parent = <&plic0>; }; serial0: serial@f0300000 { compatible = "andestech,uart16550", "ns16550a"; reg = <0x0 0xf0300000 0x0 0x1000>; interrupts = <9 4>; clock-frequency = <19660800>; reg-shift = <2>; reg-offset = <32>; no-loopback-test = <1>; interrupt-parent = <&plic0>; }; mac0: mac@e0100000 { compatible = "andestech,atmac100"; reg = <0x0 0xe0100000 0x0 0x1000>; interrupts = <19 4>; interrupt-parent = <&plic0>; }; mmc0: mmc@f0e00000 { compatible = "andestech,atfsdc010"; max-frequency = <100000000>; clock-freq-min-max = <400000 100000000>; fifo-depth = <0x10>; reg = <0x0 0xf0e00000 0x0 0x1000>; interrupts = <18 4>; cap-sd-highspeed; interrupt-parent = <&plic0>; }; dma0: dma@f0c00000 { compatible = "andestech,atcdmac300"; reg = <0x0 0xf0c00000 0x0 0x1000>; interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; dma-channels = <8>; interrupt-parent = <&plic0>; }; lcd0: lcd@e0200000 { compatible = "andestech,atflcdc100"; reg = <0x0 0xe0200000 0x0 0x1000>; interrupts = <20 4>; interrupt-parent = <&plic0>; }; smc0: smc@e0400000 { compatible = "andestech,atfsmc020"; reg = <0x0 0xe0400000 0x0 0x1000>; }; snd0: snd@f0d00000 { compatible = "andestech,atfac97"; reg = <0x0 0xf0d00000 0x0 0x1000>; interrupts = <17 4>; interrupt-parent = <&plic0>; }; pmu { compatible = "riscv,base-pmu"; }; virtio_mmio@fe007000 { interrupts = <0x17 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe007000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe006000 { interrupts = <0x16 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe006000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe005000 { interrupts = <0x15 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe005000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe004000 { interrupts = <0x14 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe004000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe003000 { interrupts = <0x13 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe003000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe002000 { interrupts = <0x12 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe002000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe001000 { interrupts = <0x11 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe001000 0x0 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@fe000000 { interrupts = <0x10 0x4>; interrupt-parent = <0x2>; reg = <0x0 0xfe000000 0x0 0x1000>; compatible = "virtio,mmio"; }; nor@0,0 { #address-cells = <2>; #size-cells = <2>; compatible = "cfi-flash"; reg = <0x0 0x88000000 0x0 0x4000000>; bank-width = <2>; device-width = <1>; }; spi: spi@f0b00000 { compatible = "andestech,atcspi200"; reg = <0x0 0xf0b00000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; clocks = <&spiclk>; interrupts = <4 4>; interrupt-parent = <&plic0>; flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; spi-cpol; spi-cpha; }; }; }; |