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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 | // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2005-2009 * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> * * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ #include <config.h> #include <command.h> #include <asm/global_data.h> #include "asm/m5282.h" #include <bmp_layout.h> #include <env.h> #include <init.h> #include <bus_vcxk.h> /*---------------------------------------------------------------------------*/ DECLARE_GLOBAL_DATA_PTR; /*---------------------------------------------------------------------------*/ int checkboard (void) { puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n"); #if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) puts(" Boot from Internal FLASH\n"); #endif return 0; } int dram_init(void) { int size, i; size = 0; MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | MCFSDRAMC_DCR_RC((15 * CFG_SYS_CLK / 1000000) >> 4); asm (" nop"); #ifdef CFG_SYS_SDRAM_BASE0 MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)| MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32; asm (" nop"); MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V; asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; asm (" nop"); for (i = 0; i < 10; i++) asm (" nop"); *(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; asm (" nop"); for (i = 0; i < 2000; i++) asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; asm (" nop"); /* write SDRAM mode register */ *(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; asm (" nop"); size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024; #endif #ifdef CFG_SYS_SDRAM_BASE1xx MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; *(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; for (i = 0; i < 2000; i++) asm (" nop"); MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; *(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024; #endif gd->ram_size = size; return 0; } #if defined(CFG_SYS_DRAM_TEST) int testdram(void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); for (p = pstart; p < pend; p++) *p = 0xaaaaaaaa; for (p = pstart; p < pend; p++) { if (*p != 0xaaaaaaaa) { printf ("SDRAM test fails at: %08x\n", (uint) p); return 1; } } printf("SDRAM test phase 2:\n"); for (p = pstart; p < pend; p++) *p = 0x55555555; for (p = pstart; p < pend; p++) { if (*p != 0x55555555) { printf ("SDRAM test fails at: %08x\n", (uint) p); return 1; } } printf("SDRAM test passed.\n"); return 0; } #endif #if defined(CONFIG_HW_WATCHDOG) void hw_watchdog_init(void) { char *s; int enable; enable = 1; s = env_get("watchdog"); if (s != NULL) if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0)) enable = 0; if (enable) MCFGPTA_GPTDDR |= (1<<2); else MCFGPTA_GPTDDR &= ~(1<<2); } void hw_watchdog_reset(void) { MCFGPTA_GPTPORT ^= (1<<2); } #endif int misc_init_r(void) { #ifdef CONFIG_HW_WATCHDOG hw_watchdog_init(); #endif return 1; } /*---------------------------------------------------------------------------*/ /* EOF EB+MCF-EV123.c */ |