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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017 Andes Technology Corporation * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ #include <config.h> #include <cpu_func.h> #include <env.h> #include <flash.h> #include <image.h> #include <init.h> #include <net.h> #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) #include <netdev.h> #endif #include <asm/csr.h> #include <asm/global_data.h> #include <asm/sbi.h> #include <linux/io.h> #include <faraday/ftsmc020.h> #include <fdtdec.h> #include <dm.h> #include <spl.h> DECLARE_GLOBAL_DATA_PTR; /* * Miscellaneous platform dependent initializations */ #if IS_ENABLED(CONFIG_MISC_INIT_R) int misc_init_r(void) { long csr_marchid = 0; const long mask_64 = 0x8000; const long mask_cpu = 0xff; char cpu_name[10] = {}; #if CONFIG_IS_ENABLED(RISCV_SMODE) sbi_get_marchid(&csr_marchid); #elif CONFIG_IS_ENABLED(RISCV_MMODE) csr_marchid = csr_read(CSR_MARCHID); #endif if (mask_64 & csr_marchid) snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu & csr_marchid)); else snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid)); return env_set("cpu", cpu_name); } #endif int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; return 0; } int dram_init(void) { return fdtdec_setup_mem_size_base(); } int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) int board_eth_init(struct bd_info *bd) { return ftmac100_initialize(bd); } #endif ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) { return 0; } #define ANDES_HW_DTB_ADDRESS 0xF2000000 int board_fdt_blob_setup(void **fdtp) { if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) { *fdtp = (void *)(ulong)gd->arch.firmware_fdt_addr; return 0; } } if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC) { *fdtp = (void *)CONFIG_SYS_FDT_BASE; return 0; } return -EINVAL; } #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init() { /* enable andes-l2 cache */ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) enable_caches(); } #endif int smc_init(void) { int node = -1; const char *compat = "andestech,atfsmc020"; void *blob = (void *)gd->fdt_blob; fdt_addr_t addr; struct ftsmc020_bank *regs; node = fdt_node_offset_by_compatible(blob, -1, compat); if (node < 0) return -FDT_ERR_NOTFOUND; addr = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", 0, NULL, false); if (addr == FDT_ADDR_T_NONE) return -EINVAL; regs = (struct ftsmc020_bank *)(uintptr_t)addr; regs->cr &= ~FTSMC020_BANK_WPROT; return 0; } #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { smc_init(); return 0; } #endif #ifdef CONFIG_SPL void board_boot_order(u32 *spl_boot_list) { u8 i; u32 boot_devices[] = { #ifdef CONFIG_SPL_RAM_SUPPORT BOOT_DEVICE_RAM, #endif #ifdef CONFIG_SPL_MMC BOOT_DEVICE_MMC1, #endif }; for (i = 0; i < ARRAY_SIZE(boot_devices); i++) spl_boot_list[i] = boot_devices[i]; } #endif #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { /* boot using first FIT config */ return 0; } #endif |