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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 | // SPDX-License-Identifier: GPL-2.0+ /** * (C) Copyright 2014, Cavium Inc. **/ #include <config.h> #include <cpu_func.h> #include <dm.h> #include <init.h> #include <malloc.h> #include <errno.h> #include <net.h> #include <asm/global_data.h> #include <linux/compiler.h> #include <cavium/atf.h> #include <asm/armv8/mmu.h> #if !CONFIG_IS_ENABLED(OF_CONTROL) #include <dm/platform_data/serial_pl01x.h> static const struct pl01x_serial_plat serial0 = { .base = CFG_SYS_SERIAL0, .type = TYPE_PL011, .clock = 0, .skip_init = true, }; U_BOOT_DRVINFO(thunderx_serial0) = { .name = "serial_pl01x", .plat = &serial0, }; static const struct pl01x_serial_plat serial1 = { .base = CFG_SYS_SERIAL1, .type = TYPE_PL011, .clock = 0, .skip_init = true, }; U_BOOT_DRVINFO(thunderx_serial1) = { .name = "serial_pl01x", .plat = &serial1, }; #endif DECLARE_GLOBAL_DATA_PTR; static struct mm_region thunderx_mem_map[] = { { .virt = 0x000000000000UL, .phys = 0x000000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE, }, { .virt = 0x800000000000UL, .phys = 0x800000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE, }, { .virt = 0x840000000000UL, .phys = 0x840000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE, }, { /* List terminator */ 0, } }; struct mm_region *mem_map = thunderx_mem_map; int timer_init(void) { return 0; } int dram_init(void) { ssize_t node_count = atf_node_count(); ssize_t dram_size; int node; printf("Initializing\nNodes in system: %zd\n", node_count); gd->ram_size = 0; for (node = 0; node < node_count; node++) { dram_size = atf_dram_size(node); printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20); gd->ram_size += dram_size; } gd->ram_size -= MEM_BASE; *(unsigned long *)CPU_RELEASE_ADDR = 0; puts("DRAM size:"); return 0; } /* * Board specific reset that is system reset. */ void reset_cpu(void) { } /* * Board specific ethernet initialization routine. */ int board_eth_init(struct bd_info *bis) { int rc = 0; return rc; } |