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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. */ #include <errno.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> #ifndef CONFIG_DM_PMIC_PFUZE100 int pfuze_mode_init(struct pmic *p, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; pmic_reg_read(p, PFUZE100_DEVICEID, &id); id = id & 0xf; if (id == 0) { switch_num = 6; offset = PFUZE100_SW1CMODE; } else if (id == 1) { switch_num = 4; offset = PFUZE100_SW2MODE; } else { printf("Not supported, id=%d\n", id); return -EINVAL; } ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); return ret; } } return ret; } struct pmic *pfuze_common_init(unsigned char i2cbus) { struct pmic *p; int ret; unsigned int reg; ret = power_pfuze100_init(i2cbus); if (ret) return NULL; p = pmic_get("PFUZE100"); ret = pmic_probe(p); if (ret) return NULL; pmic_reg_read(p, PFUZE100_DEVICEID, ®); printf("PMIC: PFUZE100 ID=0x%02x\n", reg); /* Set SW1AB stanby volage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ pmic_reg_read(p, PFUZE100_SW1CCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; pmic_reg_write(p, PFUZE100_SW1CCONF, reg); return p; } #elif defined(CONFIG_DM_PMIC) int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { switch_num = 6; offset = PFUZE100_SW1CMODE; } else if (id == 1) { switch_num = 4; offset = PFUZE100_SW2MODE; } else { printf("Not supported, id=%d\n", id); return -EINVAL; } ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); return ret; } } return ret; } struct udevice *pfuze_common_init(void) { struct udevice *dev; int ret; unsigned int reg, dev_id, rev_id; ret = pmic_get("pfuze100@8", &dev); if (ret == -ENODEV) return NULL; dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); rev_id = pmic_reg_read(dev, PFUZE100_REVID); printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* Set SW1AB stanby volage to 0.975V */ reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); return dev; } #endif |