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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. */ #include <config.h> #include <fdt_support.h> #include <net.h> #include <asm/io.h> #include <netdev.h> #include <fm_eth.h> #include <fsl_dtsec.h> #include <fsl_mdio.h> #include <malloc.h> #include "../common/fman.h" int board_eth_init(struct bd_info *bis) { #ifdef CONFIG_FMAN_ENET int i; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; u32 srds_s1; struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); /* Set the two on-board SGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); /* Set the on-board AQ PHY address */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); switch (srds_s1) { case 0x1133: break; default: printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", srds_s1); break; } dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); /* 10GBase-R on lane A, MAC 9 */ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); cpu_eth_init(bis); #endif return pci_eth_init(bis); } #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) { u32 srds_s1; int i, prop; int offset, nodeoff; const char *path; struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; /* Cycle through all aliases */ for (prop = 0; ; prop++) { const char *name; /* FDT might have been edited, recompute the offset */ offset = fdt_first_property_offset(blob, fdt_path_offset(blob, "/aliases") ); /* Select property number 'prop' */ for (i = 0; i < prop; i++) offset = fdt_next_property_offset(blob, offset); if (offset < 0) break; path = fdt_getprop_by_offset(blob, offset, &name, NULL); nodeoff = fdt_path_offset(blob, path); switch (srds_s1) { case 0x1133: if (!strcmp(name, "ethernet0")) fdt_status_disabled(blob, nodeoff); if (!strcmp(name, "ethernet1")) fdt_status_disabled(blob, nodeoff); break; default: printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n", __func__, srds_s1); break; } } return 0; } #endif |