Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 | Overview -------- The LX2160A Reference Design (RDB) is a high-performance computing, evaluation, and development platform that supports the QorIQ LX2160A Layerscape Architecture processor and its personalities. LX2160A SoC Overview -------------------------------------- For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc LX2160ARDB board Overview ---------------------- DDR Memory Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Data rate upto 3.2 GT/s. SERDES ports Thress serdes controllers (24 lanes) Serdes1: Supports two USXGMII connectors, each connected through Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi CS4223 phy. Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0 connectors Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector eSDHC eSDHC1: Supports a SD connector for connecting SD cards eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC Octal SPI (XSPI) Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator for off-board emulation I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer Serial Ports USB 3.0 Two high speed USB 3.0 ports. First USB 3.0 port configured as Host with Type-A connector, second USB 3.0 port configured as OTG with micro-AB connector Serial Ports Two UART ports Ethernet Two RGMII interfaces Debug ARM JTAG support Booting Options --------------- a) Flexspi boot b) SD boot Memory map for Flexspi flash ---------------------------- Image Flash Offset bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 fip.bin (bl31 + bl33(u-boot) + header for Secure-boot(secure-boot only)) 0x00100000 Boot firmware Environment 0x00500000 DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 DPAA2 MC Firmware 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Memory map for sd card ---------------------------- Image SD card Offset bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 fip.bin (bl31 + bl33(u-boot) + header for Secure-boot(secure-boot only)) 0x00800 Boot firmware Environment 0x02800 DDR PHY Firmware (fip_ddr_all.bin) 0x04000 DPAA2 MC Firmware 0x05000 DPAA2 DPL 0x06800 DPAA2 DPC 0x07000 Kernel.itb 0x08000 LX2160AQDS board Overview ---------------------- Various Mezzanine cards and their connection for different SERDES protocols is as below: SERDES1 |CARDS ----------------------------------------------------------------------- 1 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 3 |Mezzanine:X-M11-USXGMII (29828) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 7 |Mezzanine:X-M11-USXGMII (29828) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 8 |Mezzanine:X-M12-XFI (29829) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) |Mezzanine:X-M12-XFI (29829) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 13 |Mezzanine:X-M8-100G (29734) |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) |Mezzanine:X-M8-100G (29734) |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 15 |Mezzanine:X-M8-100G (29734) |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 17 |Mezzanine:X-M13-25G (32133) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 19 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) |Mezzanine:X-M7-40G (29738) |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ 20 |Mezzanine:X-M7-40G (29738) |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J108) |Mezzanine:X-M7-40G (29738) |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111) |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------ SERDES2 |CARDS ----------------------------------------------------------------------- 2 |Mezzanine:X-M6-PCIE-X8 (29737) * |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT3(J116) ------------------------------------------------------------------------ 3 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect I/O cable to IO_SLOT3(J116) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------ 5 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect I/O cable to IO_SLOT3(J116) |Mezzanine:X-M5-SATA (29687) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------ 11 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect I/O cable to IO_SLOT7(J127) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT8(J131) ------------------------------------------------------------------------ SERDES3 |CARDS ----------------------------------------------------------------------- 2 |Mezzanine:X-M6-PCIE-X8 (29737) * |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120) |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123) |Connect I/O cable to IO_SLOT5(J122) ------------------------------------------------------------------------- 3 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120) |Connect I/O cable to IO_SLOT5(J122) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123) |Connect I/O cable to IO_SLOT6(J125) ------------------------------------------------------------------------- LX2162A SoC Overview -------------------------------------- For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc LX2162AQDS board Overview ---------------------- DDR Memory One ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Data rate upto 2.9 GT/s. SERDES ports Two serdes controllers (12 lanes) Serdes1: Supports two USXGMII connectors, each connected through Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi CS4223 phy. Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector, four SATA 3.0 connectors eSDHC eSDHC1: Supports a SD connector for connecting SD cards eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC Octal SPI (XSPI) Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator for off-board emulation I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer Serial Ports USB 3.0 One high speed USB 3.0 ports. First USB 3.0 port configured as Host with Type-A connector, second USB 3.0 port configured as OTG with micro-AB connector Serial Ports Two UART ports Ethernet Two RGMII interfaces Debug ARM JTAG support Booting Options --------------- a) Flexspi boot b) SD boot c) eMMC boot Memory map for Flexspi flash ---------------------------- Image Flash Offset bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 fip.bin (bl31 + bl33(u-boot) + header for Secure-boot(secure-boot only)) 0x00100000 Boot firmware Environment 0x00500000 DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 DPAA2 MC Firmware 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Memory map for sd/eMMC card ---------------------------- Image SD/eMMC card Offset bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 fip.bin (bl31 + bl33(u-boot) + header for Secure-boot(secure-boot only)) 0x00800 Boot firmware Environment 0x02800 DDR PHY Firmware (fip_ddr_all.bin) 0x04000 DPAA2 MC Firmware 0x05000 DPAA2 DPL 0x06800 DPAA2 DPC 0x07000 Kernel.itb 0x08000 Various Mezzanine cards and their connection for different SERDES protocols is as below: SERDES1 |CARDS ----------------------------------------------------------------------- 1 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------ 3 |Mezzanine:X-M11-USXGMII (29828) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------ 15 |Mezzanine:X-M8-50G (29734) |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------ 17 |Mezzanine:X-M13-25G (32133) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------ 18 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) ------------------------------------------------------------------------ 20 |Mezzanine:X-M7-40G (29738) |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) |Connect I/O cable to IO_SLOT1(J108) ------------------------------------------------------------------------ SERDES2 |CARDS ----------------------------------------------------------------------- 2 |Mezzanine:X-M6-PCIE-X8 (29737) * |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT3(J116) ------------------------------------------------------------------------ 3 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect I/O cable to IO_SLOT3(J116) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------ 5 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect I/O cable to IO_SLOT3(J116) |Mezzanine:X-M5-SATA (29687) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------ 11 |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) |Connect I/O cable to IO_SLOT7(J127) |Mezzanine:X-M4-PCIE-SGMII (29733) |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) |Connect I/O cable to IO_SLOT8(J131) ------------------------------------------------------------------------ |