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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2017 NXP */ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <log.h> #include <asm/arch/soc.h> #include <asm/arch/clock.h> #include <asm/global_data.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) { int vdd; vdd = get_core_volt_from_fuse(); /* Nothing to do for silicons doesn't support VID */ if (vdd < 0) return; if (vdd == 900) { popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; debug("VID: configure DDR to support 900 mV\n"); } } #endif void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; /* * we use identical timing for all slots. If needed, change the code * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; */ pbsp = udimms[0]; /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { if (pbsp->n_ranks == pdimm->n_ranks) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; goto found; } pbsp_highest = pbsp; } pbsp++; } if (pbsp_highest) { printf("Error: board specific timing not found for %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; } else { panic("DIMM is not supported by this board"); } found: debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, pbsp->wrlvl_ctl_3); popts->half_strength_driver_enable = 0; /* * Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; /* Enable ZQ calibration */ popts->zq_en = 1; /* Enable DDR hashing */ popts->addr_hash = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) fsl_ddr_setup_0v9_volt(popts); #endif popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; } #ifdef CONFIG_TFABOOT int fsl_initdram(void) { gd->ram_size = tfa_get_dram_size(); if (!gd->ram_size) gd->ram_size = fsl_ddr_sdram_size(); return 0; } #else int fsl_initdram(void) { puts("Initializing DDR....using SPD\n"); #if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); #else gd->ram_size = fsl_ddr_sdram(); #endif return 0; } #endif /* CONFIG_TFABOOT */ |