Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 | /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright(C) 2020 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> */ #include <clk.h> #include <clk-uclass.h> #include <dm.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <dt-bindings/clock/imxrt1020-clock.h> #include "clk.h" static struct clk_ops imxrt1020_clk_ops = { .set_rate = ccf_clk_set_rate, .get_rate = ccf_clk_get_rate, .enable = ccf_clk_enable, .disable = ccf_clk_disable, }; static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", }; static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", }; static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", }; static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; static int imxrt1020_clk_probe(struct udevice *dev) { void *base; /* Anatop clocks */ base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); clk_dm(IMXRT1020_CLK_PLL2_SYS, imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "osc", base + 0x30, 0x1)); clk_dm(IMXRT1020_CLK_PLL3_USB_OTG, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x1)); /* PLL bypass out */ clk_dm(IMXRT1020_CLK_PLL2_BYPASS, imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1020_CLK_PLL3_BYPASS, imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT)); clk_dm(IMXRT1020_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0)); clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M, imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1)); clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2)); clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M, imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3)); clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M, imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1)); clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M, imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3)); /* CCM clocks */ base = dev_read_addr_ptr(dev); if (base == (void *)FDT_ADDR_T_NONE) return -EINVAL; clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL, imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels))); clk_dm(IMXRT1020_CLK_PERIPH_SEL, imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMXRT1020_CLK_USDHC1_SEL, imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1020_CLK_USDHC2_SEL, imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); clk_dm(IMXRT1020_CLK_LPUART_SEL, imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1, lpuart_sels, ARRAY_SIZE(lpuart_sels))); clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL, imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1, semc_alt_sels, ARRAY_SIZE(semc_alt_sels))); clk_dm(IMXRT1020_CLK_SEMC_SEL, imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1, semc_sels, ARRAY_SIZE(semc_sels))); clk_dm(IMXRT1020_CLK_AHB_PODF, imx_clk_divider(dev, "ahb_podf", "periph_sel", base + 0x14, 10, 3)); clk_dm(IMXRT1020_CLK_USDHC1_PODF, imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); clk_dm(IMXRT1020_CLK_USDHC2_PODF, imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3)); clk_dm(IMXRT1020_CLK_LPUART_PODF, imx_clk_divider(dev, "lpuart_podf", "lpuart_sel", base + 0x24, 0, 6)); clk_dm(IMXRT1020_CLK_SEMC_PODF, imx_clk_divider(dev, "semc_podf", "semc_sel", base + 0x14, 16, 3)); clk_dm(IMXRT1020_CLK_USDHC1, imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMXRT1020_CLK_USDHC2, imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4)); clk_dm(IMXRT1020_CLK_LPUART1, imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24)); clk_dm(IMXRT1020_CLK_SEMC, imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4)); #ifdef CONFIG_XPL_BUILD struct clk *clk, *clk1; clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1); clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk); clk_set_parent(clk1, clk); /* Configure PLL3_USB_OTG to 480MHz */ clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk); clk_enable(clk); clk_set_rate(clk, 480000000UL); clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1); clk_set_parent(clk1, clk); clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk); clk_set_rate(clk, 297000000UL); clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk); clk_enable(clk); clk_set_rate(clk, 528000000UL); clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1); clk_set_parent(clk1, clk); #endif return 0; } static const struct udevice_id imxrt1020_clk_ids[] = { { .compatible = "fsl,imxrt1020-ccm" }, { }, }; U_BOOT_DRIVER(imxrt1020_clk) = { .name = "clk_imxrt1020", .id = UCLASS_CLK, .of_match = imxrt1020_clk_ids, .ops = &imxrt1020_clk_ops, .probe = imxrt1020_clk_probe, .flags = DM_FLAG_PRE_RELOC, }; |