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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2025 Microchip Technology Inc. * Eoin Dickson <eoin.dickson@microchip.com> */ #include <dm.h> #include <asm-generic/gpio.h> #include <asm/io.h> #include <errno.h> #include <asm/gpio.h> #include <linux/bitops.h> #define MPFS_INP_REG 0x84 #define COREGPIO_INP_REG 0x90 #define MPFS_OUTP_REG 0x88 #define COREGPIO_OUTP_REG 0xA0 #define MPFS_GPIO_CTRL(i) (0x4 * (i)) #define MPFS_MAX_NUM_GPIO 32 #define MPFS_GPIO_EN_OUT_BUF BIT(2) #define MPFS_GPIO_EN_IN BIT(1) #define MPFS_GPIO_EN_OUT BIT(0) struct mpfs_gpio_reg_offsets { u8 inp; u8 outp; }; struct mchp_gpio_plat { void *base; const struct mpfs_gpio_reg_offsets *regs; }; static void mchp_update_gpio_reg(void *bptr, u32 offset, bool value) { void __iomem *ptr = (void __iomem *)bptr; u32 old = readl(ptr); if (value) writel(old | offset, ptr); else writel(old & ~offset, ptr); } static int mchp_gpio_direction_input(struct udevice *dev, u32 offset) { struct mchp_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); if (offset > uc_priv->gpio_count) return -EINVAL; mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_IN, true); mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT, false); mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT_BUF, false); return 0; } static int mchp_gpio_direction_output(struct udevice *dev, u32 offset, int value) { struct mchp_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); if (offset > uc_priv->gpio_count) return -EINVAL; mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_IN, false); mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT, true); mchp_update_gpio_reg(plat->base + MPFS_GPIO_CTRL(offset), MPFS_GPIO_EN_OUT_BUF, true); mchp_update_gpio_reg(plat->base + plat->regs->outp, BIT(offset), value); return 0; } static int mchp_gpio_get_value(struct udevice *dev, u32 offset) { struct mchp_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); int val, input; if (offset > uc_priv->gpio_count) return -EINVAL; input = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_IN; if (input) val = (readl(plat->base + plat->regs->inp) & BIT(offset)); else val = (readl(plat->base + plat->regs->outp) & BIT(offset)); return val >> offset; } static int mchp_gpio_set_value(struct udevice *dev, u32 offset, int value) { struct mchp_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); if (offset > uc_priv->gpio_count) return -EINVAL; mchp_update_gpio_reg(plat->base + plat->regs->outp, BIT(offset), value); return 0; } static int mchp_gpio_get_function(struct udevice *dev, unsigned int offset) { struct mchp_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); u32 outdir, indir, val; if (offset > uc_priv->gpio_count) return -EINVAL; /* Get direction of the pin */ outdir = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_OUT; indir = readl(plat->base + MPFS_GPIO_CTRL(offset)) & MPFS_GPIO_EN_IN; if (outdir) val = GPIOF_OUTPUT; else if (indir) val = GPIOF_INPUT; else val = GPIOF_UNUSED; return val; } static int mchp_gpio_probe(struct udevice *dev) { struct mchp_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); char name[18], *str; plat->regs = (struct mpfs_gpio_reg_offsets *)dev_get_driver_data(dev); sprintf(name, "gpio@%4lx_", (uintptr_t)plat->base); str = strdup(name); if (!str) return -ENOMEM; uc_priv->bank_name = str; uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", MPFS_MAX_NUM_GPIO); return 0; } static const struct mpfs_gpio_reg_offsets mpfs_reg_offsets = { .inp = MPFS_INP_REG, .outp = MPFS_OUTP_REG, }; static const struct mpfs_gpio_reg_offsets coregpio_reg_offsets = { .inp = COREGPIO_INP_REG, .outp = COREGPIO_OUTP_REG, }; static const struct udevice_id mchp_gpio_match[] = { { .compatible = "microchip,mpfs-gpio", .data = (unsigned long)&mpfs_reg_offsets, }, { .compatible = "microchip,coregpio-rtl-v3", .data = (unsigned long)&coregpio_reg_offsets, }, { /* end of list */ } }; static const struct dm_gpio_ops mchp_gpio_ops = { .direction_input = mchp_gpio_direction_input, .direction_output = mchp_gpio_direction_output, .get_value = mchp_gpio_get_value, .set_value = mchp_gpio_set_value, .get_function = mchp_gpio_get_function, }; static int mchp_gpio_of_to_plat(struct udevice *dev) { struct mchp_gpio_plat *plat = dev_get_plat(dev); plat->base = dev_read_addr_ptr(dev); if (!plat->base) return -EINVAL; return 0; } U_BOOT_DRIVER(gpio_mpfs) = { .name = "gpio_mpfs", .id = UCLASS_GPIO, .of_match = mchp_gpio_match, .of_to_plat = of_match_ptr(mchp_gpio_of_to_plat), .plat_auto = sizeof(struct mchp_gpio_plat), .ops = &mchp_gpio_ops, .probe = mchp_gpio_probe, }; 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