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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 | // SPDX-License-Identifier: GPL-2.0+ /* * SiFive GPIO driver * * Copyright (C) 2019 SiFive, Inc. */ #include <dm.h> #include <asm/arch/gpio.h> #include <asm/io.h> #include <errno.h> #include <asm/gpio.h> #include <linux/bitops.h> static int sifive_gpio_probe(struct udevice *dev) { struct sifive_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); char name[18], *str; sprintf(name, "gpio@%4lx_", (uintptr_t)plat->base); str = strdup(name); if (!str) return -ENOMEM; uc_priv->bank_name = str; /* * Use the gpio count mentioned in device tree, * if not specified in dt, set NR_GPIOS as default */ uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", NR_GPIOS); return 0; } static void sifive_update_gpio_reg(void *bptr, u32 offset, bool value) { void __iomem *ptr = (void __iomem *)bptr; u32 bit = BIT(offset); u32 old = readl(ptr); if (value) writel(old | bit, ptr); else writel(old & ~bit, ptr); } static int sifive_gpio_direction_input(struct udevice *dev, u32 offset) { struct sifive_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); if (offset > uc_priv->gpio_count) return -EINVAL; /* Configure gpio direction as input */ sifive_update_gpio_reg(plat->base + GPIO_INPUT_EN, offset, true); sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_EN, offset, false); return 0; } static int sifive_gpio_direction_output(struct udevice *dev, u32 offset, int value) { struct sifive_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); if (offset > uc_priv->gpio_count) return -EINVAL; /* Configure gpio direction as output */ sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_EN, offset, true); sifive_update_gpio_reg(plat->base + GPIO_INPUT_EN, offset, false); /* Set the output state of the pin */ sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_VAL, offset, value); return 0; } static int sifive_gpio_get_value(struct udevice *dev, u32 offset) { struct sifive_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); int val; int dir; if (offset > uc_priv->gpio_count) return -EINVAL; /* Get direction of the pin */ dir = !(readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset)); if (dir) val = readl(plat->base + GPIO_INPUT_VAL) & BIT(offset); else val = readl(plat->base + GPIO_OUTPUT_VAL) & BIT(offset); return val ? HIGH : LOW; } static int sifive_gpio_set_value(struct udevice *dev, u32 offset, int value) { struct sifive_gpio_plat *plat = dev_get_plat(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); if (offset > uc_priv->gpio_count) return -EINVAL; sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_VAL, offset, value); return 0; } static int sifive_gpio_get_function(struct udevice *dev, unsigned int offset) { struct sifive_gpio_plat *plat = dev_get_plat(dev); u32 outdir, indir, val; struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); if (offset > uc_priv->gpio_count) return -1; /* Get direction of the pin */ outdir = readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset); indir = readl(plat->base + GPIO_INPUT_EN) & BIT(offset); if (outdir) /* Pin at specified offset is configured as output */ val = GPIOF_OUTPUT; else if (indir) /* Pin at specified offset is configured as input */ val = GPIOF_INPUT; else /*The requested GPIO is not set as input or output */ val = GPIOF_UNUSED; return val; } static const struct udevice_id sifive_gpio_match[] = { { .compatible = "sifive,gpio0" }, { } }; static const struct dm_gpio_ops sifive_gpio_ops = { .direction_input = sifive_gpio_direction_input, .direction_output = sifive_gpio_direction_output, .get_value = sifive_gpio_get_value, .set_value = sifive_gpio_set_value, .get_function = sifive_gpio_get_function, }; static int sifive_gpio_of_to_plat(struct udevice *dev) { struct sifive_gpio_plat *plat = dev_get_plat(dev); plat->base = dev_read_addr_ptr(dev); if (!plat->base) return -EINVAL; return 0; } U_BOOT_DRIVER(gpio_sifive) = { .name = "gpio_sifive", .id = UCLASS_GPIO, .of_match = sifive_gpio_match, .of_to_plat = of_match_ptr(sifive_gpio_of_to_plat), .plat_auto = sizeof(struct sifive_gpio_plat), .ops = &sifive_gpio_ops, .probe = sifive_gpio_probe, }; |