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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 | // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com> */ #include <log.h> #include <asm/io.h> #include <clk.h> #include <dm.h> #include <i2c.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/err.h> #define I2C_TIMEOUT_MS 100 /* Control register fields */ #define REG_CTRL_START BIT(0) #define REG_CTRL_ACK_IGNORE BIT(1) #define REG_CTRL_STATUS BIT(2) #define REG_CTRL_ERROR BIT(3) #define REG_CTRL_CLKDIV_SHIFT 12 #define REG_CTRL_CLKDIV_MASK GENMASK(21, 12) #define REG_CTRL_CLKDIVEXT_SHIFT 28 #define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28) enum { TOKEN_END = 0, TOKEN_START, TOKEN_SLAVE_ADDR_WRITE, TOKEN_SLAVE_ADDR_READ, TOKEN_DATA, TOKEN_DATA_LAST, TOKEN_STOP, }; struct i2c_regs { u32 ctrl; u32 slave_addr; u32 tok_list0; u32 tok_list1; u32 tok_wdata0; u32 tok_wdata1; u32 tok_rdata0; u32 tok_rdata1; }; struct meson_i2c_data { unsigned char div_factor; }; struct meson_i2c { const struct meson_i2c_data *data; struct clk clk; struct i2c_regs *regs; struct i2c_msg *msg; /* Current I2C message */ bool last; /* Whether the message is the last */ uint count; /* Number of bytes in the current transfer */ uint pos; /* Position of current transfer in message */ u32 tokens[2]; /* Sequence of tokens to be written */ uint num_tokens; /* Number of tokens to be written */ }; static void meson_i2c_reset_tokens(struct meson_i2c *i2c) { i2c->tokens[0] = 0; i2c->tokens[1] = 0; i2c->num_tokens = 0; } static void meson_i2c_add_token(struct meson_i2c *i2c, int token) { if (i2c->num_tokens < 8) i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4); else i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4); i2c->num_tokens++; } /* * Retrieve data for the current transfer (which can be at most 8 * bytes) from the device internal buffer. */ static void meson_i2c_get_data(struct meson_i2c *i2c, u8 *buf, int len) { u32 rdata0, rdata1; int i; rdata0 = readl(&i2c->regs->tok_rdata0); rdata1 = readl(&i2c->regs->tok_rdata1); debug("meson i2c: read data %08x %08x len %d\n", rdata0, rdata1, len); for (i = 0; i < min(4, len); i++) *buf++ = (rdata0 >> i * 8) & 0xff; for (i = 4; i < min(8, len); i++) *buf++ = (rdata1 >> (i - 4) * 8) & 0xff; } /* * Write data for the current transfer (which can be at most 8 bytes) * to the device internal buffer. */ static void meson_i2c_put_data(struct meson_i2c *i2c, u8 *buf, int len) { u32 wdata0 = 0, wdata1 = 0; int i; for (i = 0; i < min(4, len); i++) wdata0 |= *buf++ << (i * 8); for (i = 4; i < min(8, len); i++) wdata1 |= *buf++ << ((i - 4) * 8); writel(wdata0, &i2c->regs->tok_wdata0); writel(wdata1, &i2c->regs->tok_wdata1); debug("meson i2c: write data %08x %08x len %d\n", wdata0, wdata1, len); } /* * Prepare the next transfer: pick the next 8 bytes in the remaining * part of message and write tokens and data (if needed) to the * device. */ static void meson_i2c_prepare_xfer(struct meson_i2c *i2c) { bool write = !(i2c->msg->flags & I2C_M_RD); int i; i2c->count = min(i2c->msg->len - i2c->pos, 8u); for (i = 0; i + 1 < i2c->count; i++) meson_i2c_add_token(i2c, TOKEN_DATA); if (i2c->count) { if (write || i2c->pos + i2c->count < i2c->msg->len) meson_i2c_add_token(i2c, TOKEN_DATA); else meson_i2c_add_token(i2c, TOKEN_DATA_LAST); } if (write) meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count); if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len) meson_i2c_add_token(i2c, TOKEN_STOP); writel(i2c->tokens[0], &i2c->regs->tok_list0); writel(i2c->tokens[1], &i2c->regs->tok_list1); } static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg) { int token; token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ : TOKEN_SLAVE_ADDR_WRITE; writel(msg->addr << 1, &i2c->regs->slave_addr); meson_i2c_add_token(i2c, TOKEN_START); meson_i2c_add_token(i2c, token); } static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg, int last) { ulong start; debug("meson i2c: %s addr %u len %u\n", (msg->flags & I2C_M_RD) ? "read" : "write", msg->addr, msg->len); i2c->msg = msg; i2c->last = last; i2c->pos = 0; i2c->count = 0; meson_i2c_reset_tokens(i2c); meson_i2c_do_start(i2c, msg); do { meson_i2c_prepare_xfer(i2c); /* start the transfer */ setbits_le32(&i2c->regs->ctrl, REG_CTRL_START); start = get_timer(0); while (readl(&i2c->regs->ctrl) & REG_CTRL_STATUS) { if (get_timer(start) > I2C_TIMEOUT_MS) { clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START); debug("meson i2c: timeout\n"); return -ETIMEDOUT; } udelay(1); } meson_i2c_reset_tokens(i2c); clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START); if (readl(&i2c->regs->ctrl) & REG_CTRL_ERROR) { debug("meson i2c: error\n"); return -EREMOTEIO; } if ((msg->flags & I2C_M_RD) && i2c->count) { meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, i2c->count); } i2c->pos += i2c->count; } while (i2c->pos < msg->len); return 0; } static int meson_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) { struct meson_i2c *i2c = dev_get_priv(bus); int i, ret = 0; for (i = 0; i < nmsgs; i++) { ret = meson_i2c_xfer_msg(i2c, msg + i, i == nmsgs - 1); if (ret) return ret; } return 0; } static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) { struct meson_i2c *i2c = dev_get_priv(bus); ulong clk_rate; unsigned int div; clk_rate = clk_get_rate(&i2c->clk); if (IS_ERR_VALUE(clk_rate)) return -EINVAL; div = DIV_ROUND_UP(clk_rate, speed * i2c->data->div_factor); /* clock divider has 12 bits */ if (div >= (1 << 12)) { debug("meson i2c: requested bus frequency too low\n"); div = (1 << 12) - 1; } clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIV_MASK, (div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT); clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIVEXT_MASK, (div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT); debug("meson i2c: set clk %u, src %lu, div %u\n", speed, clk_rate, div); return 0; } static int meson_i2c_probe(struct udevice *bus) { struct meson_i2c *i2c = dev_get_priv(bus); int ret; i2c->data = (const struct meson_i2c_data *)dev_get_driver_data(bus); ret = clk_get_by_index(bus, 0, &i2c->clk); if (ret < 0) return ret; ret = clk_enable(&i2c->clk); if (ret) return ret; i2c->regs = dev_read_addr_ptr(bus); clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START); return 0; } static const struct dm_i2c_ops meson_i2c_ops = { .xfer = meson_i2c_xfer, .set_bus_speed = meson_i2c_set_bus_speed, }; static const struct meson_i2c_data i2c_meson6_data = { .div_factor = 4, }; static const struct meson_i2c_data i2c_gxbb_data = { .div_factor = 4, }; static const struct meson_i2c_data i2c_axg_data = { .div_factor = 3, }; static const struct udevice_id meson_i2c_ids[] = { {.compatible = "amlogic,meson6-i2c", .data = (ulong)&i2c_meson6_data}, {.compatible = "amlogic,meson-gx-i2c", .data = (ulong)&i2c_gxbb_data}, {.compatible = "amlogic,meson-gxbb-i2c", .data = (ulong)&i2c_gxbb_data}, {.compatible = "amlogic,meson-axg-i2c", .data = (ulong)&i2c_axg_data}, {} }; U_BOOT_DRIVER(i2c_meson) = { .name = "i2c_meson", .id = UCLASS_I2C, .of_match = meson_i2c_ids, .probe = meson_i2c_probe, .priv_auto = sizeof(struct meson_i2c), .ops = &meson_i2c_ops, }; |