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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 | // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2009 Industrie Dial Face S.p.A. * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com> * * (C) Copyright 2001 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. */ /* * This provides a bit-banged interface to the ethernet MII management * channel. */ #include <ioports.h> #include <ppc_asm.tmpl> #include <miiphy.h> #include <asm/global_data.h> /***************************************************************************** * * Utility to send the preamble, address, and register (common to read * and write). */ static void miiphy_pre(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, char read, unsigned char addr, unsigned char reg) { int j; /* * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. * The IEEE spec says this is a PHY optional requirement. The AMD * 79C874 requires one after power up and one after a MII communications * error. This means that we are doing more preambles than we need, * but it is safer and will be much more robust. */ ops->mdio_active(miidev); ops->set_mdio(miidev, 1); for (j = 0; j < 32; j++) { ops->set_mdc(miidev, 0); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); } /* send the start bit (01) and the read opcode (10) or write (10) */ ops->set_mdc(miidev, 0); ops->set_mdio(miidev, 0); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); ops->set_mdc(miidev, 0); ops->set_mdio(miidev, 1); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); ops->set_mdc(miidev, 0); ops->set_mdio(miidev, read); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); ops->set_mdc(miidev, 0); ops->set_mdio(miidev, !read); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); /* send the PHY address */ for (j = 0; j < 5; j++) { ops->set_mdc(miidev, 0); if ((addr & 0x10) == 0) { ops->set_mdio(miidev, 0); } else { ops->set_mdio(miidev, 1); } ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); addr <<= 1; } /* send the register address */ for (j = 0; j < 5; j++) { ops->set_mdc(miidev, 0); if ((reg & 0x10) == 0) { ops->set_mdio(miidev, 0); } else { ops->set_mdio(miidev, 1); } ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); reg <<= 1; } } /***************************************************************************** * * Read a MII PHY register. * * Returns: * 0 on success */ int bb_miiphy_read(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, int addr, int devad, int reg) { unsigned short rdreg; /* register working value */ int v; int j; /* counter */ miiphy_pre(miidev, ops, 1, addr, reg); /* tri-state our MDIO I/O pin so we can read */ ops->set_mdc(miidev, 0); ops->mdio_tristate(miidev); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); /* check the turnaround bit: the PHY should be driving it to zero */ ops->get_mdio(miidev, &v); if (v != 0) { /* puts ("PHY didn't drive TA low\n"); */ for (j = 0; j < 32; j++) { ops->set_mdc(miidev, 0); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); } /* There is no PHY, return */ return -1; } ops->set_mdc(miidev, 0); ops->delay(miidev); /* read 16 bits of register data, MSB first */ rdreg = 0; for (j = 0; j < 16; j++) { ops->set_mdc(miidev, 1); ops->delay(miidev); rdreg <<= 1; ops->get_mdio(miidev, &v); rdreg |= (v & 0x1); ops->set_mdc(miidev, 0); ops->delay(miidev); } ops->set_mdc(miidev, 1); ops->delay(miidev); ops->set_mdc(miidev, 0); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg); return rdreg; } /***************************************************************************** * * Write a MII PHY register. * * Returns: * 0 on success */ int bb_miiphy_write(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops, int addr, int devad, int reg, u16 value) { int j; /* counter */ miiphy_pre(miidev, ops, 0, addr, reg); /* send the turnaround (10) */ ops->set_mdc(miidev, 0); ops->set_mdio(miidev, 1); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); ops->set_mdc(miidev, 0); ops->set_mdio(miidev, 0); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); /* write 16 bits of register data, MSB first */ for (j = 0; j < 16; j++) { ops->set_mdc(miidev, 0); if ((value & 0x00008000) == 0) { ops->set_mdio(miidev, 0); } else { ops->set_mdio(miidev, 1); } ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); value <<= 1; } /* * Tri-state the MDIO line. */ ops->mdio_tristate(miidev); ops->set_mdc(miidev, 0); ops->delay(miidev); ops->set_mdc(miidev, 1); ops->delay(miidev); return 0; } |