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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018 Marvell International Ltd. * * https://spdx.org/licenses */ #include <dm.h> #include <errno.h> #include <fdtdec.h> #include <log.h> #include <malloc.h> #include <pci.h> #include <asm/global_data.h> #include <asm/io.h> #include <linux/ioport.h> DECLARE_GLOBAL_DATA_PTR; /* * This driver supports multiple types of operations / host bridges / busses: * * OTX_ECAM: Octeon TX & TX2 ECAM (Enhanced Configuration Access Mechanism) * Used to access the internal on-chip devices which are connected * to internal buses * OTX_PEM: Octeon TX PEM (PCI Express MAC) * Used to access the external (off-chip) PCI devices * OTX2_PEM: Octeon TX2 PEM (PCI Express MAC) * Used to access the external (off-chip) PCI devices */ enum { OTX_ECAM, OTX_PEM, OTX2_PEM, }; /** * struct octeontx_pci - Driver private data * @type: Device type matched via compatible (e.g. OTX_ECAM etc) * @cfg: Config resource * @bus: Bus resource */ struct octeontx_pci { unsigned int type; struct resource cfg; struct resource bus; }; static ulong readl_size(uintptr_t addr, enum pci_size_t size) { ulong val; switch (size) { case PCI_SIZE_8: val = readb(addr); break; case PCI_SIZE_16: val = readw(addr); break; case PCI_SIZE_32: val = readl(addr); break; default: printf("Invalid size\n"); return -EINVAL; }; return val; } static void writel_size(uintptr_t addr, enum pci_size_t size, ulong valuep) { switch (size) { case PCI_SIZE_8: writeb(valuep, addr); break; case PCI_SIZE_16: writew(valuep, addr); break; case PCI_SIZE_32: writel(valuep, addr); break; default: printf("Invalid size\n"); }; } static bool octeontx_bdf_invalid(pci_dev_t bdf) { if (PCI_BUS(bdf) == 1 && PCI_DEV(bdf) > 0) return true; return false; } static int octeontx_ecam_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); *valuep = readl_size(pcie->cfg.start + address, size); debug("%02x.%02x.%02x: u%d %x -> %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep); return 0; } static int octeontx_ecam_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + pcie->bus.start - hose->first_busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); writel_size(pcie->cfg.start + address, size, value); debug("%02x.%02x.%02x: u%d %x <- %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, value); return 0; } static int octeontx_pem_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; u8 hdrtype; u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0); *valuep = pci_conv_32_to_size(~0UL, offset, size); if (octeontx_bdf_invalid(bdf)) return -EPERM; address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4; *valuep = readl_size(pcie->cfg.start + address + offset, size); hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE); if (hdrtype == PCI_HEADER_TYPE_BRIDGE && offset >= PCI_PRIMARY_BUS && offset <= PCI_SUBORDINATE_BUS && *valuep != pci_conv_32_to_size(~0UL, offset, size)) *valuep -= pci_conv_32_to_size(bus_offs, offset, size); return 0; } static int octeontx_pem_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; u8 hdrtype; u8 pri_bus = pcie->bus.start + 1 - hose->first_busno; u32 bus_offs = (pri_bus << 16) | (pri_bus << 8) | (pri_bus << 0); address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, PCI_DEV(bdf), PCI_FUNC(bdf), 0) << 4; hdrtype = readb(pcie->cfg.start + address + PCI_HEADER_TYPE); if (hdrtype == PCI_HEADER_TYPE_BRIDGE && offset >= PCI_PRIMARY_BUS && offset <= PCI_SUBORDINATE_BUS && value != pci_conv_32_to_size(~0UL, offset, size)) value += pci_conv_32_to_size(bus_offs, offset, size); if (octeontx_bdf_invalid(bdf)) return -EPERM; writel_size(pcie->cfg.start + address + offset, size, value); debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, address, value); return 0; } static int octeontx2_pem_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; *valuep = pci_conv_32_to_size(~0UL, offset, size); if (octeontx_bdf_invalid(bdf)) return -EPERM; address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); *valuep = readl_size(pcie->cfg.start + address, size); debug("%02x.%02x.%02x: u%d %x (%lx) -> %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, address, *valuep); return 0; } static int octeontx2_pem_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); struct pci_controller *hose = dev_get_uclass_priv(bus); uintptr_t address; if (octeontx_bdf_invalid(bdf)) return -EPERM; address = PCIE_ECAM_OFFSET(PCI_BUS(bdf) + 1 - hose->first_busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); writel_size(pcie->cfg.start + address, size, value); debug("%02x.%02x.%02x: u%d %x (%lx) <- %lx\n", PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, address, value); return 0; } int pci_octeontx_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); int ret = -EIO; switch (pcie->type) { case OTX_ECAM: ret = octeontx_ecam_read_config(bus, bdf, offset, valuep, size); break; case OTX_PEM: ret = octeontx_pem_read_config(bus, bdf, offset, valuep, size); break; case OTX2_PEM: ret = octeontx2_pem_read_config(bus, bdf, offset, valuep, size); break; } return ret; } int pci_octeontx_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(bus); int ret = -EIO; switch (pcie->type) { case OTX_ECAM: ret = octeontx_ecam_write_config(bus, bdf, offset, value, size); break; case OTX_PEM: ret = octeontx_pem_write_config(bus, bdf, offset, value, size); break; case OTX2_PEM: ret = octeontx2_pem_write_config(bus, bdf, offset, value, size); break; } return ret; } static int pci_octeontx_of_to_plat(struct udevice *dev) { return 0; } static int pci_octeontx_probe(struct udevice *dev) { struct octeontx_pci *pcie = (struct octeontx_pci *)dev_get_priv(dev); int err; pcie->type = dev_get_driver_data(dev); err = dev_read_resource(dev, 0, &pcie->cfg); if (err) { debug("Error reading resource: %s\n", fdt_strerror(err)); return err; } err = dev_read_pci_bus_range(dev, &pcie->bus); if (err) { debug("Error reading resource: %s\n", fdt_strerror(err)); return err; } return 0; } static const struct dm_pci_ops pci_octeontx_ops = { .read_config = pci_octeontx_read_config, .write_config = pci_octeontx_write_config, }; static const struct udevice_id pci_octeontx_ids[] = { { .compatible = "cavium,pci-host-thunder-ecam", .data = OTX_ECAM }, { .compatible = "cavium,pci-host-octeontx-ecam", .data = OTX_ECAM }, { .compatible = "pci-host-ecam-generic", .data = OTX_ECAM }, { .compatible = "cavium,pci-host-thunder-pem", .data = OTX_PEM }, { .compatible = "marvell,pci-host-octeontx2-pem", .data = OTX2_PEM }, { } }; U_BOOT_DRIVER(pci_octeontx) = { .name = "pci_octeontx", .id = UCLASS_PCI, .of_match = pci_octeontx_ids, .ops = &pci_octeontx_ops, .of_to_plat = pci_octeontx_of_to_plat, .probe = pci_octeontx_probe, .priv_auto = sizeof(struct octeontx_pci), .flags = DM_FLAG_PRE_RELOC, }; |