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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 | // SPDX-License-Identifier: GPL-2.0+ /* * Allwinner sun50i(H6) USB 3.0 phy driver * * Copyright (C) 2020 Samuel Holland <samuel@sholland.org> * * Based on the Linux driver, which is: * * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> * * Based on phy-sun9i-usb.c, which is: * * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org> * * Based on code from Allwinner BSP, which is: * * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. */ #include <asm/io.h> #include <clk.h> #include <dm.h> #include <dm/device_compat.h> #include <generic-phy.h> #include <linux/bitops.h> #include <reset.h> /* Interface Status and Control Registers */ #define SUNXI_ISCR 0x00 #define SUNXI_PIPE_CLOCK_CONTROL 0x14 #define SUNXI_PHY_TUNE_LOW 0x18 #define SUNXI_PHY_TUNE_HIGH 0x1c #define SUNXI_PHY_EXTERNAL_CONTROL 0x20 /* USB2.0 Interface Status and Control Register */ #define SUNXI_ISCR_FORCE_VBUS (3 << 12) /* PIPE Clock Control Register */ #define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) /* PHY External Control Register */ #define SUNXI_PEC_EXTERN_VBUS (3 << 1) #define SUNXI_PEC_SSC_EN (1 << 24) #define SUNXI_PEC_REF_SSP_EN (1 << 26) /* PHY Tune High Register */ #define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) #define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) #define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) #define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) #define SUNXI_TX_SWING_FULL(n) ((n) << 6) #define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) #define SUNXI_LOS_BIAS(n) ((n) << 3) #define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) #define SUNXI_TXVBOOSTLVL(n) ((n) << 0) #define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0) struct sun50i_usb3_phy_priv { void __iomem *regs; struct reset_ctl reset; struct clk clk; }; static void sun50i_usb3_phy_open(struct sun50i_usb3_phy_priv *phy) { u32 val; val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); val |= SUNXI_PEC_EXTERN_VBUS; val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); val |= SUNXI_PCC_PIPE_CLK_OPEN; writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); val = readl(phy->regs + SUNXI_ISCR); val |= SUNXI_ISCR_FORCE_VBUS; writel(val, phy->regs + SUNXI_ISCR); /* * All the magic numbers written to the PHY_TUNE_{LOW_HIGH} * registers are directly taken from the BSP USB3 driver from * Allwiner. */ writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | SUNXI_TX_DEEMPH_3P5DB_MASK); val |= SUNXI_TXVBOOSTLVL(0x7); val |= SUNXI_LOS_BIAS(0x7); val |= SUNXI_TX_SWING_FULL(0x55); val |= SUNXI_TX_DEEMPH_6DB(0x20); val |= SUNXI_TX_DEEMPH_3P5DB(0x15); writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); } static int sun50i_usb3_phy_init(struct phy *phy) { struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev); int ret; ret = clk_prepare_enable(&priv->clk); if (ret) return ret; ret = reset_deassert(&priv->reset); if (ret) { clk_disable_unprepare(&priv->clk); return ret; } sun50i_usb3_phy_open(priv); return 0; } static int sun50i_usb3_phy_exit(struct phy *phy) { struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev); reset_assert(&priv->reset); clk_disable_unprepare(&priv->clk); return 0; } static const struct phy_ops sun50i_usb3_phy_ops = { .init = sun50i_usb3_phy_init, .exit = sun50i_usb3_phy_exit, }; static int sun50i_usb3_phy_probe(struct udevice *dev) { struct sun50i_usb3_phy_priv *priv = dev_get_priv(dev); int ret; ret = clk_get_by_index(dev, 0, &priv->clk); if (ret) { dev_err(dev, "failed to get phy clock\n"); return ret; } ret = reset_get_by_index(dev, 0, &priv->reset); if (ret) { dev_err(dev, "failed to get reset control\n"); return ret; } priv->regs = dev_read_addr_ptr(dev); if (!priv->regs) return -EINVAL; return 0; } static const struct udevice_id sun50i_usb3_phy_ids[] = { { .compatible = "allwinner,sun50i-h6-usb3-phy" }, { }, }; U_BOOT_DRIVER(sun50i_usb3_phy) = { .name = "sun50i-usb3-phy", .id = UCLASS_PHY, .of_match = sun50i_usb3_phy_ids, .ops = &sun50i_usb3_phy_ops, .probe = sun50i_usb3_phy_probe, .priv_auto = sizeof(struct sun50i_usb3_phy_priv), }; |