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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Microsemi SoCs pinctrl driver * * Author: <alexandre.belloni@free-electrons.com> * Author: <gregory.clement@bootlin.com> * License: Dual MIT/GPL * Copyright (c) 2017 Microsemi Corporation */ #include <asm/gpio.h> #include <asm/system.h> #include <config.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/device_compat.h> #include <dm/devres.h> #include <dm/lists.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <errno.h> #include <fdtdec.h> #include <linux/bitops.h> #include <linux/io.h> #include "mscc-common.h" static void mscc_writel(unsigned int offset, void *addr) { if (offset < 32) writel(BIT(offset), addr); else writel(BIT(offset % 32), addr + 4); } static unsigned int mscc_readl(unsigned int offset, void *addr) { if (offset < 32) return readl(addr); else return readl(addr + 4); } static void mscc_setbits(unsigned int offset, void *addr) { if (offset < 32) writel(readl(addr) | BIT(offset), addr); else writel(readl(addr + 4) | BIT(offset % 32), addr + 4); } static void mscc_clrbits(unsigned int offset, void *addr) { if (offset < 32) writel(readl(addr) & ~BIT(offset), addr); else writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4); } static int mscc_get_functions_count(struct udevice *dev) { struct mscc_pinctrl *info = dev_get_priv(dev); return info->num_func; } static const char *mscc_get_function_name(struct udevice *dev, unsigned int function) { struct mscc_pinctrl *info = dev_get_priv(dev); return info->function_names[function]; } static int mscc_pin_function_idx(unsigned int pin, unsigned int function, const struct mscc_pin_data *mscc_pins) { struct mscc_pin_caps *p = mscc_pins[pin].drv_data; int i; for (i = 0; i < MSCC_FUNC_PER_PIN; i++) { if (function == p->functions[i]) return i; } return -1; } static int mscc_pinmux_set_mux(struct udevice *dev, unsigned int pin_selector, unsigned int selector) { struct mscc_pinctrl *info = dev_get_priv(dev); struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data; int f, offset, regoff; f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins); if (f < 0) return -EINVAL; /* * f is encoded on two bits. * bit 0 of f goes in BIT(pin) of ALT0, bit 1 of f goes in BIT(pin) of * ALT1 * This is racy because both registers can't be updated at the same time * but it doesn't matter much for now. */ offset = pin->pin; regoff = info->mscc_gpios[MSCC_GPIO_ALT0]; if (offset >= 32) { offset = offset % 32; regoff = info->mscc_gpios[MSCC_GPIO_ALT1]; } if (f & BIT(0)) mscc_setbits(offset, info->regs + regoff); else mscc_clrbits(offset, info->regs + regoff); if (f & BIT(1)) mscc_setbits(offset, info->regs + regoff + 4); else mscc_clrbits(offset, info->regs + regoff + 4); return 0; } static int mscc_pctl_get_groups_count(struct udevice *dev) { struct mscc_pinctrl *info = dev_get_priv(dev); return info->num_pins; } static const char *mscc_pctl_get_group_name(struct udevice *dev, unsigned int group) { struct mscc_pinctrl *info = dev_get_priv(dev); return info->mscc_pins[group].name; } static int mscc_create_group_func_map(struct udevice *dev, struct mscc_pinctrl *info) { u16 pins[info->num_pins]; int f, npins, i; for (f = 0; f < info->num_func; f++) { for (npins = 0, i = 0; i < info->num_pins; i++) { if (mscc_pin_function_idx(i, f, info->mscc_pins) >= 0) pins[npins++] = i; } info->func[f].ngroups = npins; info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *), GFP_KERNEL); if (!info->func[f].groups) return -ENOMEM; for (i = 0; i < npins; i++) info->func[f].groups[i] = info->mscc_pins[pins[i]].name; } return 0; } static int mscc_pinctrl_register(struct udevice *dev, struct mscc_pinctrl *info) { int ret; ret = mscc_create_group_func_map(dev, info); if (ret) { dev_err(dev, "Unable to create group func map.\n"); return ret; } return 0; } static int mscc_gpio_get(struct udevice *dev, unsigned int offset) { struct mscc_pinctrl *info = dev_get_priv(dev->parent); unsigned int val; if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) & BIT(offset % 32)) val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OUT]); else val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_IN]); return !!(val & BIT(offset % 32)); } static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value) { struct mscc_pinctrl *info = dev_get_priv(dev->parent); if (value) mscc_writel(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]); else mscc_writel(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]); return 0; } static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset) { struct mscc_pinctrl *info = dev_get_priv(dev->parent); unsigned int val; val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]); return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT; } static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset) { struct mscc_pinctrl *info = dev_get_priv(dev->parent); mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]); return 0; } static int mscc_gpio_direction_output(struct udevice *dev, unsigned int offset, int value) { struct mscc_pinctrl *info = dev_get_priv(dev->parent); mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]); return mscc_gpio_set(dev, offset, value); } const struct dm_gpio_ops mscc_gpio_ops = { .set_value = mscc_gpio_set, .get_value = mscc_gpio_get, .get_function = mscc_gpio_get_direction, .direction_input = mscc_gpio_direction_input, .direction_output = mscc_gpio_direction_output, }; const struct pinctrl_ops mscc_pinctrl_ops = { .get_pins_count = mscc_pctl_get_groups_count, .get_pin_name = mscc_pctl_get_group_name, .get_functions_count = mscc_get_functions_count, .get_function_name = mscc_get_function_name, .pinmux_set = mscc_pinmux_set_mux, .set_state = pinctrl_generic_set_state, }; int mscc_pinctrl_probe(struct udevice *dev, int num_func, const struct mscc_pin_data *mscc_pins, int num_pins, char * const *function_names, const unsigned long *mscc_gpios) { struct mscc_pinctrl *priv = dev_get_priv(dev); int ret; priv->regs = dev_remap_addr(dev); if (!priv->regs) return -EINVAL; priv->func = devm_kzalloc(dev, num_func * sizeof(struct mscc_pmx_func), GFP_KERNEL); priv->num_func = num_func; priv->mscc_pins = mscc_pins; priv->num_pins = num_pins; priv->function_names = function_names; priv->mscc_gpios = mscc_gpios; ret = mscc_pinctrl_register(dev, priv); return ret; } |