Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2019 NXP */ #include <fdtdec.h> #include <errno.h> #include <dm.h> #include <dm/device_compat.h> #include <dm/lists.h> #include <i2c.h> #include <log.h> #include <asm/global_data.h> #include <linux/delay.h> #include <linux/printk.h> #include <power/pmic.h> #include <power/regulator.h> #include <power/pca9450.h> #include <sysreset.h> DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, { .prefix = "B", .driver = PCA9450_REGULATOR_DRIVER}, /* ldo */ { .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER}, { .prefix = "L", .driver = PCA9450_REGULATOR_DRIVER}, { }, }; static int pca9450_reg_count(struct udevice *dev) { return PCA9450_REG_NUM; } static int pca9450_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { pr_err("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } return 0; } static int pca9450_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { pr_err("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } return 0; } static int pca9450_bind(struct udevice *dev) { int children; ofnode regulators_node; regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { debug("%s: %s regulators subnode not found!", __func__, dev->name); return -ENXIO; } debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); children = pmic_bind_children(dev, regulators_node, pmic_children_info); if (!children) debug("%s: %s - no child found\n", __func__, dev->name); /* Always return success for this device */ return 0; } static int pca9450_probe(struct udevice *dev) { unsigned int reset_ctrl; int ret; if (CONFIG_IS_ENABLED(SYSRESET)) { ret = device_bind_driver_to_node(dev, "pca9450_sysreset", "pca9450_sysreset", dev_ofnode(dev), NULL); if (ret) return ret; } if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; else reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12; return pmic_clrsetbits(dev, PCA9450_RESET_CTRL, PCA9450_PMIC_RESET_WDOG_B_CFG_MASK, reset_ctrl); } static struct dm_pmic_ops pca9450_ops = { .reg_count = pca9450_reg_count, .read = pca9450_read, .write = pca9450_write, }; static const struct udevice_id pca9450_ids[] = { { .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, }, { .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, }, { .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, }, { .compatible = "nxp,pca9451a", .data = NXP_CHIP_TYPE_PCA9451A, }, { .compatible = "nxp,pca9452", .data = NXP_CHIP_TYPE_PCA9452, }, { } }; U_BOOT_DRIVER(pmic_pca9450) = { .name = "pca9450 pmic", .id = UCLASS_PMIC, .of_match = pca9450_ids, .bind = pca9450_bind, .probe = pca9450_probe, .ops = &pca9450_ops, }; #ifdef CONFIG_SYSRESET static int pca9450_sysreset_request(struct udevice *dev, enum sysreset_t type) { u8 cmd = PCA9450_SW_RST_COLD_RST; if (type != SYSRESET_COLD) return -EPROTONOSUPPORT; if (pmic_write(dev->parent, PCA9450_SW_RST, &cmd, 1)) { dev_err(dev, "reset command failed\n"); } else { /* tRESTART is 250ms, delay 300ms just to be sure */ mdelay(300); /* Should not get here, warn if we do */ dev_warn(dev, "didn't respond to reset command\n"); } return -EINPROGRESS; } int pca9450_sysreset_get_status(struct udevice *dev, char *buf, int size) { const char *reason; int ret; u8 reg; ret = pmic_read(dev->parent, PCA9450_PWRON_STAT, ®, 1); if (ret) return ret; switch (reg) { case PCA9450_PWRON_STAT_PWRON_MASK: reason = "PWRON"; break; case PCA9450_PWRON_STAT_WDOG_MASK: reason = "WDOGB"; break; case PCA9450_PWRON_STAT_SW_RST_MASK: reason = "SW_RST"; break; case PCA9450_PWRON_STAT_PMIC_RST_MASK: reason = "PMIC_RST"; break; default: reason = "UNKNOWN"; break; } ret = snprintf(buf, size, "Reset Status: %s\n", reason); if (ret < 0) { dev_err(dev, "Write reset status error (err = %d)\n", ret); return -EIO; } return 0; } static struct sysreset_ops pca9450_sysreset_ops = { .request = pca9450_sysreset_request, .get_status = pca9450_sysreset_get_status, }; U_BOOT_DRIVER(pca9450_sysreset) = { .name = "pca9450_sysreset", .id = UCLASS_SYSRESET, .ops = &pca9450_sysreset_ops, }; #endif /* CONFIG_SYSRESET */ |