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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2024 Renesas Electronics Corp. */ #include <asm/io.h> #include <dm.h> #include <errno.h> #include <hang.h> #include <linux/sizes.h> #include <ram.h> #include "dbsc5.h" /* AXMM */ #define AXMM_ADSPLCR0 0x4008 #define AXMM_ADSPLCR1 0x400C #define AXMM_ADSPLCR2 0x4010 #define AXMM_ADSPLCR3 0x4014 #define AXMM_MMCR 0x4300 #define AXMM_TR0CR0 0x51000 #define AXMM_TR1CR0 0x51004 #define AXMM_TR2CR0 0x51008 #define AXMM_TR3CR 0x5100C #define AXMM_TR3CR0 0x5100C #define AXMM_TR0CR1 0x51100 #define AXMM_TR1CR1 0x51104 #define AXMM_TR2CR1 0x51108 #define AXMM_TR3CR1 0x5110C #define AXMM_TR0CR2 0x51200 #define AXMM_TR1CR2 0x51204 #define AXMM_TR2CR2 0x51208 #define AXMM_TR3CR2 0x5120C #define ACTEXT_RT0_R 0xFFC50800 #define ACTEXT_RT0_W 0xFFC51800 #define ACTEXT_IR0_R 0xFF890800 #define ACTEXT_IR0_W 0xFF891800 #define ACTEXT_IR1_R 0xFF892800 #define ACTEXT_IR1_W 0xFF893800 #define SI0_RW_MAX 0xF1201110 #define SI1_RW_MAX 0xF1202110 /* DBSC */ #define DBSC_A_CH_OFFSET 0x8000 #define DBSC_D_CH_OFFSET 0x4000 #define DBSC_SYSCNT0 0x0100 #define DBSC_SYSCNT1 0x0104 #define DBSC_FCPRSCTRL 0x0110 #define DBSC_DBBUS0CNF2 0x0808 #define DBSC_DBCAM0CNF1 0x0904 #define DBSC_DBCAM0CNF2 0x0908 #define DBSC_DBCAM0CNF3 0x090C #define DBSC_DBCAMDIS 0x09FC #define DBSC_DBSCHCNT0 0x1000 #define DBSC_DBSCHSZ0 0x1010 #define DBSC_DBSCHRW0 0x1020 #define DBSC_SCFCTST2 0x1048 #define DBSC_DBSCHQOS_0_0 0x1100 #define DBSC_DBSCHQOS_0_1 0x1104 #define DBSC_DBSCHQOS_0_2 0x1108 #define DBSC_DBSCHQOS_0_3 0x110C #define DBSC_DBSCHQOS_4_0 0x1140 #define DBSC_DBSCHQOS_4_1 0x1144 #define DBSC_DBSCHQOS_4_2 0x1148 #define DBSC_DBSCHQOS_4_3 0x114C #define DBSC_DBSCHQOS_9_0 0x1190 #define DBSC_DBSCHQOS_9_1 0x1194 #define DBSC_DBSCHQOS_9_2 0x1198 #define DBSC_DBSCHQOS_9_3 0x119C #define DBSC_DBSCHQOS_12_0 0x11C0 #define DBSC_DBSCHQOS_12_1 0x11C4 #define DBSC_DBSCHQOS_12_2 0x11C8 #define DBSC_DBSCHQOS_12_3 0x11CC #define DBSC_DBSCHQOS_13_0 0x11D0 #define DBSC_DBSCHQOS_13_1 0x11D4 #define DBSC_DBSCHQOS_13_2 0x11D8 #define DBSC_DBSCHQOS_13_3 0x11DC #define DBSC_DBSCHQOS_14_0 0x11E0 #define DBSC_DBSCHQOS_14_1 0x11E4 #define DBSC_DBSCHQOS_14_2 0x11E8 #define DBSC_DBSCHQOS_14_3 0x11EC #define DBSC_DBSCHQOS_15_0 0x11F0 #define DBSC_DBSCHQOS_15_1 0x11F4 #define DBSC_DBSCHQOS_15_2 0x11F8 #define DBSC_DBSCHQOS_15_3 0x11FC /* CCI */ #define CCIQOS00 0xC020 #define CCIQOS01 0xC024 #define CCIQOS10 0xD000 #define CCIQOS11 0xD004 /* QOS */ #define QOS_FIX_QOS_BANK0 0x0 #define QOS_FIX_QOS_BANK1 0x1000 #define QOS_BE_QOS_BANK0 0x2000 #define QOS_BE_QOS_BANK1 0x3000 #define QOS_SL_INIT 0x8000 #define QOS_REF_ARS 0x8004 #define QOS_STATQC 0x8008 #define QOS_REF_ENBL 0x8044 #define QOS_BWG 0x804C #define QOS_RAS 0x10000 #define QOS_FSS 0x10048 #define QOS_RAEN 0x10018 #define QOS_DANN_LOW 0x10030 #define QOS_DANN_HIGH 0x10034 #define QOS_DANT 0x10038 #define QOS_EMS_LOW 0x10040 #define QOS_EMS_HIGH 0x10044 #define QOS_INSFC 0x10050 #define QOS_EARLYR 0x10060 #define QOS_RACNT0 0x10080 #define QOS_STATGEN0 0x10088 #define QOSWT_FIX_QOS_BANK0 0x800 #define QOSWT_FIX_QOS_BANK1 0x1800 #define QOSWT_BE_QOS_BANK0 0x2800 #define QOSWT_BE_QOS_BANK1 0x3800 #define QOSWT_WTEN 0x8030 #define QOSWT_WTREF 0x8034 #define QOSWT_WTSET0 0x8038 #define QOSWT_WTSET1 0x803C static const struct { u64 fix; u64 be; } g_qosbw_tbl[] = { { 0x000C04010000FFFF, 0x00200030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00200030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00200030004FFC01 }, { 0x000C04010000FFFF, 0x0000000000000000 }, { 0x000C04080000FFFF, 0x00200030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00200030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04100000FFFF, 0x00100030004FFC01 }, { 0x000C04100000FFFF, 0x00100030004FFC01 }, { 0x000C04100000FFFF, 0x0000000000000000 }, { 0x000C08140000FFFF, 0x00100030004FFC01 }, { 0x000C08140000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFF0, 0x0000000000000000 }, { 0x000C04100000FFFF, 0x00100030004FFC01 }, { 0x000C04100000FFFF, 0x00100030004FFC01 }, { 0x000C04100000FFFF, 0x0000000000000000 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C08140000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x001404080000FFFF, 0x00100030004FFC01 }, { 0x001404080000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x001000F0004FFC01 }, { 0x000C04010000FFFF, 0x001000F0004FFC01 }, { 0x000C04010000FFFF, 0x002000F0004FFC01 }, { 0x000C04010000FFFF, 0x002000F0004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C04200000FFFF, 0x00100030004FFC01 }, { 0x000C04100000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C144F0000FFFF, 0x00100030004FFC01 }, { 0x000C0C4F0000FFFF, 0x00100030004FFC01 }, { 0x000C0C4F0000FFFF, 0x00100030004FFC01 }, { 0x001404080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x001424870000FFFF, 0x00100030004FFC01 }, { 0x001424870000FFFF, 0x00100030004FFC01 }, { 0x000C149E0000FFFF, 0x00100030004FFC01 }, { 0x000C149E0000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x00140C050000FFFF, 0x00100030004FFC01 }, { 0x0014450E0000FFFF, 0x00100030004FFC01 }, { 0x001424870000FFFF, 0x00100030004FFC01 }, { 0x0014289E0000FFFF, 0x00000000000FFC00 }, { 0x0014289E0000FFFF, 0x00000000000FFC00 }, { 0x0014149E0000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x001004080000FFFF, 0x0000000000000000 }, { 0x001004080000FFFF, 0x0000000000000000 }, { 0x001004080000FFFF, 0x0000000000000000 }, { 0x000C00000000FFFF, 0x001000F0004FFC01 }, { 0x000C00000000FFFF, 0x001000F0004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x001404080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000C04080000FFFF, 0x00100030004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C04010000FFFF, 0x001001D0004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C04010000FFFF, 0x001001D0004FFC01 }, { 0x000000000000FFFF, 0x0000000000000000 }, { 0x000C04010000FFFF, 0x001001D0004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x001001D0004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x000C04010000FFFF, 0x00100030004FFC01 }, { 0x001404010000FFFF, 0x00100030004FFC01 } }; static const struct { u64 fix; u64 be; } g_qoswt_tbl[] = { { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x000C04050000FFFF, 0x0000000000000000 }, { 0x000C080C0000FFFF, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x000C04050000C001, 0x0000000000000000 }, { 0x000C080C0000C001, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x001424870000C001, 0x0000000000000000 }, { 0x001424870000C001, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x001424870000FFFF, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 }, { 0x0000000000000000, 0x0000000000000000 } }; struct renesas_dbsc5_qos_priv { void __iomem *regs; }; static int dbsc5_qos_dbsc_setting(struct udevice *dev) { struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); void __iomem *regs_dbsc_a, *regs_dbsc_d; unsigned int ch, nch; if (IS_ENABLED(CONFIG_R8A779G0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) nch = 2; else if (IS_ENABLED(CONFIG_R8A779H0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) nch = 1; else return -EINVAL; for (ch = 0; ch < nch; ch++) { regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET + ch * DBSC_A_CH_OFFSET; regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET + ch * DBSC_D_CH_OFFSET; /* DBSC CAM, Scheduling Setting */ writel(0x1234, regs_dbsc_d + DBSC_SYSCNT0); writel(0x1234, regs_dbsc_a + DBSC_SYSCNT0); writel(0x48218, regs_dbsc_a + DBSC_DBCAM0CNF1); writel(0x1C4, regs_dbsc_a + DBSC_DBCAM0CNF2); writel(0x3, regs_dbsc_a + DBSC_DBCAM0CNF3); if (IS_ENABLED(CONFIG_R8A779G0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 && (renesas_get_cpu_rev_integer() < 2 || (renesas_get_cpu_rev_integer() == 2 && renesas_get_cpu_rev_fraction() <= 1))) { /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */ writel(0x11, regs_dbsc_a + DBSC_DBCAMDIS); } else { writel(0x10, regs_dbsc_a + DBSC_DBCAMDIS); } writel(0xF0037, regs_dbsc_a + DBSC_DBSCHCNT0); writel(0x1, regs_dbsc_a + DBSC_DBSCHSZ0); writel(0xF7311111, regs_dbsc_a + DBSC_DBSCHRW0); writel(0x111F1FFF, regs_dbsc_a + DBSC_SCFCTST2); /* OTLINT-5579: V4H DBSC WA3 */ writel(0x7, regs_dbsc_a + DBSC_DBBUS0CNF2); /* DBSC QoS Setting */ writel(0xFFFF, regs_dbsc_a + DBSC_DBSCHQOS_0_0); writel(0x480, regs_dbsc_a + DBSC_DBSCHQOS_0_1); writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_0_2); writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_0_3); writel(0x400, regs_dbsc_a + DBSC_DBSCHQOS_4_0); writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_4_1); writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_4_2); writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_4_3); writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_9_0); writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_9_1); writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_9_2); writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_9_3); writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_12_0); writel(0x30, regs_dbsc_a + DBSC_DBSCHQOS_12_1); writel(0x20, regs_dbsc_a + DBSC_DBSCHQOS_12_2); writel(0x10, regs_dbsc_a + DBSC_DBSCHQOS_12_3); writel(0x300, regs_dbsc_a + DBSC_DBSCHQOS_13_0); writel(0x240, regs_dbsc_a + DBSC_DBSCHQOS_13_1); writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_13_2); writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_13_3); writel(0x200, regs_dbsc_a + DBSC_DBSCHQOS_14_0); writel(0x180, regs_dbsc_a + DBSC_DBSCHQOS_14_1); writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_14_2); writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_14_3); writel(0x100, regs_dbsc_a + DBSC_DBSCHQOS_15_0); writel(0xC0, regs_dbsc_a + DBSC_DBSCHQOS_15_1); writel(0x80, regs_dbsc_a + DBSC_DBSCHQOS_15_2); writel(0x40, regs_dbsc_a + DBSC_DBSCHQOS_15_3); /* Target register is only DBSC0 side. */ if (ch == 0) writel(0x1, regs_dbsc_a + DBSC_FCPRSCTRL); writel(0x1, regs_dbsc_a + DBSC_SYSCNT1); writel(0x0, regs_dbsc_d + DBSC_SYSCNT0); writel(0x0, regs_dbsc_a + DBSC_SYSCNT0); } return 0; } static int dbsc5_qos_settings_init(struct udevice *dev) { struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); void __iomem *regs_axmm = priv->regs + DBSC5_AXMM_OFFSET; void __iomem *regs_cci = priv->regs + DBSC5_CCI_OFFSET; void __iomem *regs_qos = priv->regs + DBSC5_QOS_OFFSET; int i; if (IS_ENABLED(CONFIG_R8A779G0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) { /* Address Split 2ch */ writel(0x0, regs_axmm + AXMM_ADSPLCR0); writel(0xFF1B0C, regs_axmm + AXMM_ADSPLCR1); writel(0x0, regs_axmm + AXMM_ADSPLCR2); writel(0x0, regs_axmm + AXMM_ADSPLCR3); writel(0x8000000, regs_cci + CCIQOS00); writel(0x8000000, regs_cci + CCIQOS01); if (renesas_get_cpu_rev_integer() >= 2) { writel(0x1, regs_cci + CCIQOS10); writel(0x1, regs_cci + CCIQOS11); } else { writel(0x0, regs_cci + CCIQOS10); writel(0x0, regs_cci + CCIQOS11); } /* Resource Alloc setting */ writel(0x48, regs_qos + QOS_RAS); } else if (IS_ENABLED(CONFIG_R8A779H0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) { /* Resource Alloc setting */ writel(0x30, regs_qos + QOS_RAS); } else { return -EINVAL; } writel(0x2020201, regs_qos + QOS_DANN_LOW); writel(0x4040200, regs_qos + QOS_DANN_HIGH); writel(0x181008, regs_qos + QOS_DANT); writel(0x0, regs_qos + QOS_EMS_LOW); writel(0x0, regs_qos + QOS_EMS_HIGH); writel(0xA, regs_qos + QOS_FSS); writel(0x30F0001, regs_qos + QOS_INSFC); writel(0x0, regs_qos + QOS_EARLYR); writel(0x50003, regs_qos + QOS_RACNT0); writel(0x0, regs_qos + QOS_STATGEN0); /* QoS MSTAT setting */ writel(0x70120, regs_qos + QOS_SL_INIT); writel(0x11B0000, regs_qos + QOS_REF_ARS); writel(0x12, regs_qos + QOS_REF_ENBL); writel(0x4, regs_qos + QOS_BWG); if (IS_ENABLED(CONFIG_R8A779G0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0 && (renesas_get_cpu_rev_integer() < 2 || (renesas_get_cpu_rev_integer() == 2 && renesas_get_cpu_rev_fraction() <= 1))) { /* OTLINT-5579: V4H <= rev2.1 DBSC W/A-3 */ writel(0x0, regs_axmm + AXMM_MMCR); } else { writel(0x10000, regs_axmm + AXMM_MMCR); } writel(0x3, ACTEXT_RT0_R); writel(0x3, ACTEXT_RT0_W); /* * This may be necessary, but this IP is powered off at this point: * writel(0x3, ACTEXT_IR0_R); * writel(0x3, ACTEXT_IR0_W); * writel(0x3, ACTEXT_IR1_R); * writel(0x3, ACTEXT_IR1_W); */ if (IS_ENABLED(CONFIG_R8A779G0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779G0) { writel(0x10000, regs_axmm + AXMM_TR3CR); if (renesas_get_cpu_rev_integer() >= 2) { /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */ writel(0x38, SI0_RW_MAX); writel(0x38, SI1_RW_MAX); } } if (IS_ENABLED(CONFIG_R8A779H0) && renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A779H0) { writel(0x0, regs_axmm + AXMM_TR0CR0); writel(0x0, regs_axmm + AXMM_TR1CR0); writel(0x0, regs_axmm + AXMM_TR2CR0); writel(0x0, regs_axmm + AXMM_TR3CR0); writel(0x70707070, regs_axmm + AXMM_TR0CR1); writel(0x70707070, regs_axmm + AXMM_TR1CR1); writel(0x70707070, regs_axmm + AXMM_TR2CR1); writel(0x70707070, regs_axmm + AXMM_TR3CR1); writel(0x70707070, regs_axmm + AXMM_TR0CR2); writel(0x70707070, regs_axmm + AXMM_TR1CR2); writel(0x70707070, regs_axmm + AXMM_TR2CR2); writel(0x70707070, regs_axmm + AXMM_TR3CR2); } for (i = 0U; i < ARRAY_SIZE(g_qosbw_tbl); i++) { writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK0 + (i * 8)); writeq(g_qosbw_tbl[i].fix, regs_qos + QOS_FIX_QOS_BANK1 + (i * 8)); writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK0 + (i * 8)); writeq(g_qosbw_tbl[i].be, regs_qos + QOS_BE_QOS_BANK1 + (i * 8)); } for (i = 0U; i < ARRAY_SIZE(g_qoswt_tbl); i++) { writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK0 + (i * 8)); writeq(g_qoswt_tbl[i].fix, regs_qos + QOSWT_FIX_QOS_BANK1 + (i * 8)); writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK0 + (i * 8)); writeq(g_qoswt_tbl[i].be, regs_qos + QOSWT_BE_QOS_BANK1 + (i * 8)); } /* QoS SRAM setting */ writel(0x1, regs_qos + QOS_RAEN); writel(0x2080208, regs_qos + QOSWT_WTREF); writel(0xD90050F, regs_qos + QOSWT_WTSET0); writel(0xD90050F, regs_qos + QOSWT_WTSET1); writel(0x1, regs_qos + QOSWT_WTEN); writel(0x101, regs_qos + QOS_STATQC); return 0; } static int renesas_dbsc5_qos_probe(struct udevice *dev) { int ret; /* Setting the register of DBSC4 for QoS initialize */ ret = dbsc5_qos_dbsc_setting(dev); if (ret) return ret; return dbsc5_qos_settings_init(dev); } static int renesas_dbsc5_qos_of_to_plat(struct udevice *dev) { struct renesas_dbsc5_qos_priv *priv = dev_get_priv(dev); priv->regs = dev_read_addr_ptr(dev); if (!priv->regs) return -EINVAL; return 0; } U_BOOT_DRIVER(renesas_dbsc5_qos) = { .name = "dbsc5_qos", .id = UCLASS_NOP, .of_to_plat = renesas_dbsc5_qos_of_to_plat, .probe = renesas_dbsc5_qos_probe, .priv_auto = sizeof(struct renesas_dbsc5_qos_priv), }; |