Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2023 Nuvoton Technology Corp. */ #include <dm.h> #include <reset-uclass.h> #include <asm/io.h> #include <dm/device_compat.h> struct npcm_reset_priv { void __iomem *base; }; static int npcm_reset_request(struct reset_ctl *rst) { return 0; } static int npcm_reset_free(struct reset_ctl *rst) { return 0; } static int npcm_reset_assert(struct reset_ctl *rst) { struct npcm_reset_priv *priv = dev_get_priv(rst->dev); u32 val; debug("%s: id 0x%lx, data %ld\n", __func__, rst->id, rst->data); val = readl(priv->base + rst->id); val |= BIT(rst->data); writel(val, priv->base + rst->id); return 0; } static int npcm_reset_deassert(struct reset_ctl *rst) { struct npcm_reset_priv *priv = dev_get_priv(rst->dev); u32 val; debug("%s: id 0x%lx, data %ld\n", __func__, rst->id, rst->data); val = readl(priv->base + rst->id); val &= ~BIT(rst->data); writel(val, priv->base + rst->id); return 0; } static int npcm_reset_xlate(struct reset_ctl *rst, struct ofnode_phandle_args *args) { if (args->args_count != 2) { dev_err(rst->dev, "Invalid args_count: %d\n", args->args_count); return -EINVAL; } /* Use id field as register offset and data field as reset bit positiion */ rst->id = args->args[0]; rst->data = args->args[1]; return 0; } static int npcm_reset_probe(struct udevice *dev) { struct npcm_reset_priv *priv = dev_get_priv(dev); priv->base = dev_remap_addr(dev); if (!priv->base) return -EINVAL; return 0; } static int npcm_reset_bind(struct udevice *dev) { void __iomem *reg_base; u32 *rcr_values; int num_fields; u32 reg, val; int ret, i; reg_base = dev_remap_addr(dev); if (!reg_base) return -EINVAL; /* * Set RCR initial value * The rcr-initial-values cell is <reg_offset val> */ num_fields = dev_read_size(dev, "rcr-initial-values"); if (num_fields < 2) return 0; num_fields /= sizeof(u32); if (num_fields % 2) return -EINVAL; num_fields = num_fields / 2; rcr_values = malloc(num_fields * 2 * sizeof(u32)); if (!rcr_values) return -ENOMEM; ret = dev_read_u32_array(dev, "rcr-initial-values", rcr_values, num_fields * 2); if (ret < 0) { free(rcr_values); return -EINVAL; } for (i = 0; i < num_fields; i++) { reg = rcr_values[2 * i]; val = rcr_values[2 * i + 1]; writel(val, reg_base + reg); } free(rcr_values); return 0; } static const struct udevice_id npcm_reset_ids[] = { { .compatible = "nuvoton,npcm845-reset" }, { .compatible = "nuvoton,npcm750-reset" }, { } }; struct reset_ops npcm_reset_ops = { .request = npcm_reset_request, .rfree = npcm_reset_free, .rst_assert = npcm_reset_assert, .rst_deassert = npcm_reset_deassert, .of_xlate = npcm_reset_xlate, }; U_BOOT_DRIVER(npcm_reset) = { .name = "npcm_reset", .id = UCLASS_RESET, .of_match = npcm_reset_ids, .bind = npcm_reset_bind, .probe = npcm_reset_probe, .ops = &npcm_reset_ops, .priv_auto = sizeof(struct npcm_reset_priv), }; |