Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 | // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Peter Griffin <peter.griffin@linaro.org> */ #include "stih410-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" #include <dt-bindings/gpio/gpio.h> / { aliases { bdisp0 = &bdisp0; }; usb2_picophy1: phy2 { compatible = "st,stih407-usb2-phy"; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xf8 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, <&picophyreset STIH407_PICOPHY0_RESET>; reset-names = "global", "port"; status = "disabled"; }; usb2_picophy2: phy3 { compatible = "st,stih407-usb2-phy"; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xfc 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, <&picophyreset STIH407_PICOPHY1_RESET>; reset-names = "global", "port"; status = "disabled"; }; display-subsystem { compatible = "st,sti-display-subsystem"; ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>; assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, <&clk_s_c0_flexgen CLK_COMPO_DVP>, <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, <&clk_s_d2_flexgen CLK_PIX_GDP2>, <&clk_s_d2_flexgen CLK_PIX_GDP3>, <&clk_s_d2_flexgen CLK_PIX_GDP4>; assigned-clock-parents = <0>, <0>, <0>, <&clk_s_c0_pll1 0>, <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; assigned-clock-rates = <297000000>, <297000000>, <0>, <400000000>, <400000000>; }; soc { ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, <&softreset STIH407_USB2_PORT0_SOFTRESET>; reset-names = "power", "softreset"; phys = <&usb2_picophy1>; phy-names = "usb"; status = "disabled"; }; ehci0: usb@9a03e00 { compatible = "st,st-ehci-300x"; reg = <0x9a03e00 0x100>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, <&softreset STIH407_USB2_PORT0_SOFTRESET>; reset-names = "power", "softreset"; phys = <&usb2_picophy1>; phy-names = "usb"; status = "disabled"; }; ohci1: usb@9a83c00 { compatible = "st,st-ohci-300x"; reg = <0x9a83c00 0x100>; interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; reset-names = "power", "softreset"; phys = <&usb2_picophy2>; phy-names = "usb"; status = "disabled"; }; ehci1: usb@9a83e00 { compatible = "st,st-ehci-300x"; reg = <0x9a83e00 0x100>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; reset-names = "power", "softreset"; phys = <&usb2_picophy2>; phy-names = "usb"; status = "disabled"; }; compositor: display-controller@9d11000 { compatible = "st,stih407-compositor"; reg = <0x9d11000 0x1000>; clock-names = "compo_main", "compo_aux", "pix_main", "pix_aux", "pix_gdp1", "pix_gdp2", "pix_gdp3", "pix_gdp4", "main_parent", "aux_parent"; clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, <&clk_s_c0_flexgen CLK_COMPO_DVP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, <&clk_s_d2_flexgen CLK_PIX_GDP2>, <&clk_s_d2_flexgen CLK_PIX_GDP3>, <&clk_s_d2_flexgen CLK_PIX_GDP4>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; reset-names = "compo-main", "compo-aux"; resets = <&softreset STIH407_COMPO_SOFTRESET>, <&softreset STIH407_COMPO_SOFTRESET>; st,vtg = <&vtg_main>, <&vtg_aux>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; compo_main_out: endpoint { remote-endpoint = <&tvout_in0>; }; }; port@1 { reg = <1>; compo_aux_out: endpoint { remote-endpoint = <&tvout_in1>; }; }; }; }; tvout: encoder@8d08000 { compatible = "st,stih407-tvout"; reg = <0x8d08000 0x1000>; reg-names = "tvout-reg"; reset-names = "tvout"; resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, <&clk_s_d2_flexgen CLK_TMDS_HDMI>, <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, <&clk_s_d0_flexgen CLK_PCM_0>, <&clk_s_d2_flexgen CLK_PIX_HDDAC>, <&clk_s_d2_flexgen CLK_HDDAC>; assigned-clock-parents = <&clk_s_d2_quadfs 0>, <&clk_tmdsout_hdmi>, <&clk_s_d2_quadfs 0>, <&clk_s_d0_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tvout_in0: endpoint { remote-endpoint = <&compo_main_out>; }; }; port@1 { reg = <1>; tvout_in1: endpoint { remote-endpoint = <&compo_aux_out>; }; }; port@2 { reg = <2>; tvout_out0: endpoint { remote-endpoint = <&hdmi_in>; }; }; port@3 { reg = <3>; tvout_out1: endpoint { remote-endpoint = <&hda_in>; }; }; }; }; sti_hdmi: hdmi@8d04000 { compatible = "st,stih407-hdmi"; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; #sound-dai-cells = <0>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irq"; clock-names = "pix", "tmds", "phy", "audio", "main_parent", "aux_parent"; clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, <&clk_s_d2_flexgen CLK_TMDS_HDMI>, <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, <&clk_s_d0_flexgen CLK_PCM_0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; reset-names = "hdmi"; resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; ddc = <&hdmiddc>; port { hdmi_in: endpoint { remote-endpoint = <&tvout_out0>; }; }; }; analog@8d02000 { compatible = "st,stih407-hda"; status = "disabled"; reg = <0x8d02000 0x400>, <0x92b0120 0x4>; reg-names = "hda-reg", "video-dacs-ctrl"; clock-names = "pix", "hddac", "main_parent", "aux_parent"; clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, <&clk_s_d2_flexgen CLK_HDDAC>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; port { hda_in: endpoint { remote-endpoint = <&tvout_out1>; }; }; }; hqvdp: plane@9c00000 { compatible = "st,stih407-hqvdp"; reg = <0x9C00000 0x100000>; clock-names = "hqvdp", "pix_main"; clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; reset-names = "hqvdp"; resets = <&softreset STIH407_HDQVDP_SOFTRESET>; st,vtg = <&vtg_main>; }; bdisp0:bdisp@9f10000 { compatible = "st,stih407-bdisp"; reg = <0x9f10000 0x1000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clock-names = "bdisp"; clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; }; hva@8c85000 { compatible = "st,st-hva"; reg = <0x8c85000 0x400>, <0x6000000 0x40000>; reg-names = "hva_registers", "hva_esram"; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_hva"; clocks = <&clk_s_c0_flexgen CLK_HVA>; }; thermal@91a0000 { compatible = "st,stih407-thermal"; reg = <0x91a0000 0x28>; clock-names = "thermal"; clocks = <&clk_sysin>; interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; #thermal-sensor-cells = <0>; }; cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; clocks = <&clk_sysin>; clock-names = "cec-clk"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cec-irq"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cec0_default>; resets = <&softreset STIH407_LPM_SOFTRESET>; hdmi-phandle = <&sti_hdmi>; }; gpu: gpu@9f00000 { compatible = "st,stih410-mali", "arm,mali-400"; reg = <0x9f00000 0x10000>; /* LIMA driver needs 2 clocks, use the same for both */ clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>, <&clk_s_c0_flexgen CLK_ICN_GPU>; clock-names = "bus", "core"; assigned-clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; assigned-clock-rates = <400000000>; resets = <&softreset STIH407_GPU_SOFTRESET>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3"; status = "disabled"; }; }; }; |