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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 | // SPDX-License-Identifier: GPL-2.0+ OR MIT /* * Apple T8015 "A11" SoC * * Other names: H10, "Skye" * * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> */ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/apple-aic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/apple.h> #include <dt-bindings/spmi/spmi.h> / { interrupt-parent = <&aic>; #address-cells = <2>; #size-cells = <2>; clkref: clock-ref { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "clkref"; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu_e0>; }; core1 { cpu = <&cpu_e1>; }; core2 { cpu = <&cpu_e2>; }; core3 { cpu = <&cpu_e3>; }; }; cluster1 { core0 { cpu = <&cpu_p0>; }; core1 { cpu = <&cpu_p1>; }; }; }; cpu_e0: cpu@0 { compatible = "apple,mistral"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ performance-domains = <&cpufreq_e>; operating-points-v2 = <&mistral_opp>; capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; next-level-cache = <&l2_cache_0>; i-cache-size = <0x8000>; d-cache-size = <0x8000>; }; cpu_e1: cpu@1 { compatible = "apple,mistral"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ performance-domains = <&cpufreq_e>; operating-points-v2 = <&mistral_opp>; capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; next-level-cache = <&l2_cache_0>; i-cache-size = <0x8000>; d-cache-size = <0x8000>; }; cpu_e2: cpu@2 { compatible = "apple,mistral"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ performance-domains = <&cpufreq_e>; operating-points-v2 = <&mistral_opp>; capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; next-level-cache = <&l2_cache_0>; i-cache-size = <0x8000>; d-cache-size = <0x8000>; }; cpu_e3: cpu@3 { compatible = "apple,mistral"; reg = <0x0 0x3>; cpu-release-addr = <0 0>; /* To be filled by loader */ performance-domains = <&cpufreq_e>; operating-points-v2 = <&mistral_opp>; capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; next-level-cache = <&l2_cache_0>; i-cache-size = <0x8000>; d-cache-size = <0x8000>; }; cpu_p0: cpu@10004 { compatible = "apple,monsoon"; reg = <0x0 0x10004>; cpu-release-addr = <0 0>; /* To be filled by loader */ performance-domains = <&cpufreq_p>; operating-points-v2 = <&monsoon_opp>; capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; next-level-cache = <&l2_cache_1>; i-cache-size = <0x10000>; d-cache-size = <0x10000>; }; cpu_p1: cpu@10005 { compatible = "apple,monsoon"; reg = <0x0 0x10005>; cpu-release-addr = <0 0>; /* To be filled by loader */ performance-domains = <&cpufreq_p>; operating-points-v2 = <&monsoon_opp>; capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; next-level-cache = <&l2_cache_1>; i-cache-size = <0x10000>; d-cache-size = <0x10000>; }; l2_cache_0: l2-cache-0 { compatible = "cache"; cache-level = <2>; cache-unified; cache-size = <0x100000>; }; l2_cache_1: l2-cache-1 { compatible = "cache"; cache-level = <2>; cache-unified; cache-size = <0x800000>; }; }; mistral_opp: opp-table-0 { compatible = "operating-points-v2"; opp01 { opp-hz = /bits/ 64 <300000000>; opp-level = <1>; clock-latency-ns = <1800>; }; opp02 { opp-hz = /bits/ 64 <453000000>; opp-level = <2>; clock-latency-ns = <140000>; }; opp03 { opp-hz = /bits/ 64 <672000000>; opp-level = <3>; clock-latency-ns = <105000>; }; opp04 { opp-hz = /bits/ 64 <972000000>; opp-level = <4>; clock-latency-ns = <115000>; }; opp05 { opp-hz = /bits/ 64 <1272000000>; opp-level = <5>; clock-latency-ns = <125000>; }; opp06 { opp-hz = /bits/ 64 <1572000000>; opp-level = <6>; clock-latency-ns = <135000>; }; #if 0 /* Not available until CPU deep sleep is implemented */ opp07 { opp-hz = /bits/ 64 <1680000000>; opp-level = <7>; clock-latency-ns = <135000>; turbo-mode; }; #endif }; monsoon_opp: opp-table-1 { compatible = "operating-points-v2"; opp01 { opp-hz = /bits/ 64 <300000000>; opp-level = <1>; clock-latency-ns = <1400>; }; opp02 { opp-hz = /bits/ 64 <453000000>; opp-level = <2>; clock-latency-ns = <140000>; }; opp03 { opp-hz = /bits/ 64 <853000000>; opp-level = <3>; clock-latency-ns = <110000>; }; opp04 { opp-hz = /bits/ 64 <1332000000>; opp-level = <4>; clock-latency-ns = <110000>; }; opp05 { opp-hz = /bits/ 64 <1812000000>; opp-level = <5>; clock-latency-ns = <125000>; }; opp06 { opp-hz = /bits/ 64 <2064000000>; opp-level = <6>; clock-latency-ns = <130000>; }; opp07 { opp-hz = /bits/ 64 <2304000000>; opp-level = <7>; clock-latency-ns = <140000>; }; #if 0 /* Not available until CPU deep sleep is implemented */ opp08 { opp-hz = /bits/ 64 <2376000000>; opp-level = <8>; clock-latency-ns = <140000>; turbo-mode; }; #endif }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; nonposted-mmio; ranges; cpufreq_e: performance-controller@208e20000 { compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; reg = <0x2 0x08e20000 0 0x1000>; #performance-domain-cells = <0>; }; cpufreq_p: performance-controller@208ea0000 { compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; reg = <0x2 0x08ea0000 0 0x1000>; #performance-domain-cells = <0>; }; i2c0: i2c@22e200000 { compatible = "apple,t8015-i2c", "apple,i2c"; reg = <0x2 0x2e200000 0x0 0x1000>; clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 304 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; power-domains = <&ps_i2c0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@22e204000 { compatible = "apple,t8015-i2c", "apple,i2c"; reg = <0x2 0x2e204000 0x0 0x1000>; clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 305 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; power-domains = <&ps_i2c1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@22e208000 { compatible = "apple,t8015-i2c", "apple,i2c"; reg = <0x2 0x2e208000 0x0 0x1000>; clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 306 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; power-domains = <&ps_i2c2>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@22e20c000 { compatible = "apple,t8015-i2c", "apple,i2c"; reg = <0x2 0x2e20c000 0x0 0x1000>; clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 307 IRQ_TYPE_LEVEL_HIGH>; pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; power-domains = <&ps_i2c3>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; serial0: serial@22e600000 { compatible = "apple,s5l-uart"; reg = <0x2 0x2e600000 0x0 0x4000>; reg-io-width = <4>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 282 IRQ_TYPE_LEVEL_HIGH>; /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; power-domains = <&ps_uart0>; status = "disabled"; }; aic: interrupt-controller@232100000 { compatible = "apple,t8015-aic", "apple,aic"; reg = <0x2 0x32100000 0x0 0x8000>; #interrupt-cells = <3>; interrupt-controller; power-domains = <&ps_aic>; }; pmgr: power-management@232000000 { compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; #size-cells = <1>; reg = <0x2 0x32000000 0 0x8c000>; }; dwi_bl: backlight@232200080 { compatible = "apple,t8015-dwi-bl", "apple,dwi-bl"; reg = <0x2 0x32200080 0x0 0x8>; power-domains = <&ps_dwi>; status = "disabled"; }; pinctrl_ap: pinctrl@233100000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x33100000 0x0 0x1000>; power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_ap 0 0 223>; apple,npins = <223>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 52 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 53 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 54 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 55 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 56 IRQ_TYPE_LEVEL_HIGH>; i2c0_pins: i2c0-pins { pinmux = <APPLE_PINMUX(73, 1)>, <APPLE_PINMUX(72, 1)>; }; i2c1_pins: i2c1-pins { pinmux = <APPLE_PINMUX(182, 1)>, <APPLE_PINMUX(181, 1)>; }; i2c2_pins: i2c2-pins { pinmux = <APPLE_PINMUX(4, 1)>, <APPLE_PINMUX(3, 1)>; }; i2c3_pins: i2c3-pins { pinmux = <APPLE_PINMUX(184, 1)>, <APPLE_PINMUX(183, 1)>; }; }; pinctrl_aop: pinctrl@2340f0000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x340f0000 0x0 0x4000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_aop 0 0 49>; apple,npins = <49>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 138 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 139 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 141 IRQ_TYPE_LEVEL_HIGH>; }; spmi: spmi@235180700 { compatible = "apple,t8015-spmi", "apple,t8103-spmi"; reg = <0x2 0x35180700 0x0 0x100>; #address-cells = <2>; #size-cells = <0>; }; pinctrl_nub: pinctrl@2351f0000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x351f0000 0x0 0x4000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_nub 0 0 8>; apple,npins = <8>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 169 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 170 IRQ_TYPE_LEVEL_HIGH>; }; pmgr_mini: power-management@235200000 { compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; #size-cells = <1>; reg = <0x2 0x35200000 0 0x84000>; }; wdt: watchdog@2352b0000 { compatible = "apple,t8015-wdt", "apple,wdt"; reg = <0x2 0x352b0000 0x0 0x4000>; clocks = <&clkref>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 172 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_smc: pinctrl@236024000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x36024000 0x0 0x4000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_smc 0 0 6>; apple,npins = <6>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 202 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 203 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 204 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 205 IRQ_TYPE_LEVEL_HIGH>; /* * SMC is not yet supported and accessing this pinctrl while SMC is * suspended results in a hang. */ status = "disabled"; }; ans_mbox: mbox@257008000 { compatible = "apple,t8015-asc-mailbox"; reg = <0x2 0x57008000 0x0 0x4000>; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 265 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 266 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 267 IRQ_TYPE_LEVEL_HIGH>, <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "send-empty", "send-not-empty", "recv-empty", "recv-not-empty"; #mbox-cells = <0>; power-domains = <&ps_ans2>; }; sart: iommu@259c50000 { compatible = "apple,t8015-sart"; reg = <0x2 0x59c50000 0x0 0x10000>; power-domains = <&ps_ans2>; }; nvme@259cc0000 { compatible = "apple,t8015-nvme-ans2"; reg = <0x2 0x59cc0000 0x0 0x40000>, <0x2 0x59d20000 0x0 0x2000>; reg-names = "nvme", "ans"; interrupt-parent = <&aic>; interrupts = <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>; mboxes = <&ans_mbox>; apple,sart = <&sart>; power-domains = <&ps_ans2>, <&ps_pcie>; power-domain-names = "ans", "apcie0"; resets = <&ps_ans2>; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&aic>; interrupt-names = "phys", "virt"; /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */ interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; }; }; #include "t8015-pmgr.dtsi" |