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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 | // SPDX-License-Identifier: GPL-2.0-only OR MIT #include <dt-bindings/clock/mediatek,mt7988-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt65xx.h> #include <dt-bindings/reset/mediatek,mt7988-resets.h> / { compatible = "mediatek,mt7988a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cci: cci { compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci"; clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cci", "intermediate"; operating-points-v2 = <&cci_opp>; }; cci_opp: opp-table-cci { compatible = "operating-points-v2"; opp-shared; opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-microvolt = <850000>; }; opp-660000000 { opp-hz = /bits/ 64 <660000000>; opp-microvolt = <850000>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <850000>; }; opp-1080000000 { opp-hz = /bits/ 64 <1080000000>; opp-microvolt = <900000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a73"; reg = <0x0>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; mediatek,cci = <&cci>; }; cpu1: cpu@1 { compatible = "arm,cortex-a73"; reg = <0x1>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; mediatek,cci = <&cci>; }; cpu2: cpu@2 { compatible = "arm,cortex-a73"; reg = <0x2>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; mediatek,cci = <&cci>; }; cpu3: cpu@3 { compatible = "arm,cortex-a73"; reg = <0x3>; device_type = "cpu"; enable-method = "psci"; clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, <&topckgen CLK_TOP_XTAL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; mediatek,cci = <&cci>; }; cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <850000>; }; opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <850000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <850000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <900000>; }; }; }; oscillator-40m { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; clock-output-names = "clkxtal"; }; pmu { compatible = "arm,cortex-a73-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ secmon@43000000 { reg = <0 0x43000000 0 0x50000>; no-map; }; }; soc { compatible = "simple-bus"; ranges; #address-cells = <2>; #size-cells = <2>; gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; reg = <0 0x0c000000 0 0x40000>, /* GICD */ <0 0x0c080000 0 0x200000>, /* GICR */ <0 0x0c400000 0 0x2000>, /* GICC */ <0 0x0c410000 0 0x1000>, /* GICH */ <0 0x0c420000 0 0x2000>; /* GICV */ interrupt-parent = <&gic>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>; }; infracfg: clock-controller@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; topckgen: clock-controller@1001b000 { compatible = "mediatek,mt7988-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; #clock-cells = <1>; }; watchdog: watchdog@1001c000 { compatible = "mediatek,mt7988-wdt"; reg = <0 0x1001c000 0 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; apmixedsys: clock-controller@1001e000 { compatible = "mediatek,mt7988-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; #clock-cells = <1>; }; pio: pinctrl@1001f000 { compatible = "mediatek,mt7988-pinctrl"; reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, <0 0x11d00000 0 0x1000>, <0 0x11d20000 0 0x1000>, <0 0x11e00000 0 0x1000>, <0 0x11f00000 0 0x1000>, <0 0x1000b000 0 0x1000>; reg-names = "gpio", "iocfg_tr", "iocfg_br", "iocfg_rb", "iocfg_lb", "iocfg_tl", "eint"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 84>; interrupt-controller; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; #interrupt-cells = <2>; pcie0_pins: pcie0-pins { mux { function = "pcie"; groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", "pcie_wake_n0_0"; }; }; pcie1_pins: pcie1-pins { mux { function = "pcie"; groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", "pcie_wake_n1_0"; }; }; pcie2_pins: pcie2-pins { mux { function = "pcie"; groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", "pcie_wake_n2_0"; }; }; pcie3_pins: pcie3-pins { mux { function = "pcie"; groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", "pcie_wake_n3_0"; }; }; spi1_pins: spi1-pins { mux { function = "spi"; groups = "spi1"; }; }; uart0_pins: uart0-pins { mux { function = "uart"; groups = "uart0"; }; }; }; pwm: pwm@10048000 { compatible = "mediatek,mt7988-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, <&infracfg CLK_INFRA_66M_PWM_HCK>, <&infracfg CLK_INFRA_66M_PWM_CK1>, <&infracfg CLK_INFRA_66M_PWM_CK2>, <&infracfg CLK_INFRA_66M_PWM_CK3>, <&infracfg CLK_INFRA_66M_PWM_CK4>, <&infracfg CLK_INFRA_66M_PWM_CK5>, <&infracfg CLK_INFRA_66M_PWM_CK6>, <&infracfg CLK_INFRA_66M_PWM_CK7>, <&infracfg CLK_INFRA_66M_PWM_CK8>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; #pwm-cells = <2>; status = "disabled"; }; mcusys: mcusys@100e0000 { compatible = "mediatek,mt7988-mcusys", "syscon"; reg = <0 0x100e0000 0 0x1000>; #clock-cells = <1>; }; serial0: serial@11000000 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000000 0 0x100>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uart", "wakeup"; clocks = <&topckgen CLK_TOP_UART_SEL>, <&infracfg CLK_INFRA_52M_UART0_CK>; clock-names = "baud", "bus"; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "disabled"; }; serial@11000100 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000100 0 0x100>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uart", "wakeup"; clocks = <&topckgen CLK_TOP_UART_SEL>, <&infracfg CLK_INFRA_52M_UART1_CK>; clock-names = "baud", "bus"; status = "disabled"; }; serial@11000200 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000200 0 0x100>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uart", "wakeup"; clocks = <&topckgen CLK_TOP_UART_SEL>, <&infracfg CLK_INFRA_52M_UART2_CK>; clock-names = "baud", "bus"; status = "disabled"; }; i2c0: i2c@11003000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11003000 0 0x1000>, <0 0x10217080 0 0x80>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@11004000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11004000 0 0x1000>, <0 0x10217100 0 0x80>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@11005000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11005000 0 0x1000>, <0 0x10217180 0 0x80>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi0: spi@11007000 { compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; reg = <0 0x11007000 0 0x100>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_MPLL_D2>, <&topckgen CLK_TOP_SPI_SEL>, <&infracfg CLK_INFRA_104M_SPI0>, <&infracfg CLK_INFRA_66M_SPI0_HCK>; clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi1: spi@11008000 { compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; reg = <0 0x11008000 0 0x100>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_MPLL_D2>, <&topckgen CLK_TOP_SPIM_MST_SEL>, <&infracfg CLK_INFRA_104M_SPI1>, <&infracfg CLK_INFRA_66M_SPI1_HCK>; clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; status = "disabled"; }; spi2: spi@11009000 { compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; reg = <0 0x11009000 0 0x100>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_MPLL_D2>, <&topckgen CLK_TOP_SPI_SEL>, <&infracfg CLK_INFRA_104M_SPI2_BCK>, <&infracfg CLK_INFRA_66M_SPI2_HCK>; clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; lvts: lvts@1100a000 { compatible = "mediatek,mt7988-lvts-ap"; #thermal-sensor-cells = <1>; reg = <0 0x1100a000 0 0x1000>; clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; nvmem-cells = <&lvts_calibration>; nvmem-cell-names = "lvts-calib-data-1"; }; ssusb0: usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, <0 0x11193e00 0 0x0100>; reg-names = "mac", "ippc"; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; clocks = <&infracfg CLK_INFRA_USB_SYS>, <&infracfg CLK_INFRA_USB_REF>, <&infracfg CLK_INFRA_66M_USB_HCK>, <&infracfg CLK_INFRA_133M_USB_HCK>, <&infracfg CLK_INFRA_USB_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; phys = <&xphyu2port0 PHY_TYPE_USB2>, <&xphyu3port0 PHY_TYPE_USB3>; status = "disabled"; }; ssusb1: usb@11200000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, <&infracfg CLK_INFRA_USB_CK_P1>, <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; phys = <&tphyu2port0 PHY_TYPE_USB2>, <&tphyu3port0 PHY_TYPE_USB3>; status = "disabled"; }; mmc0: mmc@11230000 { compatible = "mediatek,mt7988-mmc"; reg = <0 0x11230000 0 0x1000>, <0 0x11D60000 0 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&infracfg CLK_INFRA_MSDC400>, <&infracfg CLK_INFRA_MSDC2_HCK>, <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, <&topckgen CLK_TOP_EMMC_400M_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, <&apmixedsys CLK_APMIXED_MSDCPLL>; clock-names = "source", "hclk", "axi_cg", "ahb_cg"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pcie2: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11280000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <3>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x20000000 0x00 0x20000000 0x00 0x00200000>, <0x82000000 0x00 0x20200000 0x00 0x20200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie2_pins>; status = "disabled"; phys = <&xphyu3port0 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc2 0>, <0 0 0 2 &pcie_intc2 1>, <0 0 0 3 &pcie_intc2 2>, <0 0 0 4 &pcie_intc2 3>; pcie_intc2: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; pcie3: pcie@11290000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11290000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <2>; interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x28000000 0x00 0x28000000 0x00 0x00200000>, <0x82000000 0x00 0x28200000 0x00 0x28200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie3_pins>; status = "disabled"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc3 0>, <0 0 0 2 &pcie_intc3 1>, <0 0 0 3 &pcie_intc3 2>, <0 0 0 4 &pcie_intc3 3>; pcie_intc3: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; pcie0: pcie@11300000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11300000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <0>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x30000000 0x00 0x30000000 0x00 0x00200000>, <0x82000000 0x00 0x30200000 0x00 0x30200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie0_pins>; status = "disabled"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, <0 0 0 2 &pcie_intc0 1>, <0 0 0 3 &pcie_intc0 2>, <0 0 0 4 &pcie_intc0 3>; pcie_intc0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; pcie1: pcie@11310000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; reg = <0 0x11310000 0 0x2000>; reg-names = "pcie-mac"; linux,pci-domain = <1>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; bus-range = <0x00 0xff>; ranges = <0x81000000 0x00 0x38000000 0x00 0x38000000 0x00 0x00200000>, <0x82000000 0x00 0x38200000 0x00 0x38200000 0x00 0x07e00000>; clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_pins>; status = "disabled"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, <0 0 0 2 &pcie_intc1 1>, <0 0 0 3 &pcie_intc1 2>, <0 0 0 4 &pcie_intc1 3>; pcie_intc1: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; tphy: t-phy@11c50000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; tphyu2port0: usb-phy@11c50000 { reg = <0 0x11c50000 0 0x700>; clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; tphyu3port0: usb-phy@11c50700 { reg = <0 0x11c50700 0 0x900>; clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; }; topmisc: system-controller@11d10084 { compatible = "mediatek,mt7988-topmisc", "syscon"; reg = <0 0x11d10084 0 0xff80>; }; xsphy: xs-phy@11e10000 { compatible = "mediatek,mt7988-xsphy", "mediatek,xsphy"; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; xphyu2port0: usb-phy@11e10000 { reg = <0 0x11e10000 0 0x400>; clocks = <&infracfg CLK_INFRA_USB_UTMI>; clock-names = "ref"; #phy-cells = <1>; }; xphyu3port0: usb-phy@11e13000 { reg = <0 0x11e13400 0 0x500>; clocks = <&infracfg CLK_INFRA_USB_PIPE>; clock-names = "ref"; #phy-cells = <1>; mediatek,syscon-type = <&topmisc 0x194 0>; }; }; xfi_tphy0: phy@11f20000 { compatible = "mediatek,mt7988-xfi-tphy"; reg = <0 0x11f20000 0 0x10000>; clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; clock-names = "xfipll", "topxtal"; resets = <&watchdog 14>; mediatek,usxgmii-performance-errata; #phy-cells = <0>; }; xfi_tphy1: phy@11f30000 { compatible = "mediatek,mt7988-xfi-tphy"; reg = <0 0x11f30000 0 0x10000>; clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; clock-names = "xfipll", "topxtal"; resets = <&watchdog 15>; #phy-cells = <0>; }; xfi_pll: clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; resets = <&watchdog 16>; #clock-cells = <1>; }; efuse@11f50000 { compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; reg = <0 0x11f50000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; soc-uuid@140 { reg = <0x140 0x10>; }; lvts_calibration: calib@918 { reg = <0x918 0x28>; }; phy_calibration_p0: calib@940 { reg = <0x940 0x10>; }; phy_calibration_p1: calib@954 { reg = <0x954 0x10>; }; phy_calibration_p2: calib@968 { reg = <0x968 0x10>; }; phy_calibration_p3: calib@97c { reg = <0x97c 0x10>; }; }; ethsys: clock-controller@15000000 { compatible = "mediatek,mt7988-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; switch: switch@15020000 { compatible = "mediatek,mt7988-switch"; reg = <0 0x15020000 0 0x8000>; interrupt-controller; #interrupt-cells = <1>; interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; ports { #address-cells = <1>; #size-cells = <0>; gsw_port0: port@0 { reg = <0>; phy-handle = <&gsw_phy0>; phy-mode = "internal"; }; gsw_port1: port@1 { reg = <1>; phy-handle = <&gsw_phy1>; phy-mode = "internal"; }; gsw_port2: port@2 { reg = <2>; phy-handle = <&gsw_phy2>; phy-mode = "internal"; }; gsw_port3: port@3 { reg = <3>; phy-handle = <&gsw_phy3>; phy-mode = "internal"; }; port@6 { reg = <6>; ethernet = <&gmac0>; phy-mode = "internal"; fixed-link { speed = <10000>; full-duplex; pause; }; }; }; mdio { #address-cells = <1>; #size-cells = <0>; mediatek,pio = <&pio>; gsw_phy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; interrupts = <0>; nvmem-cells = <&phy_calibration_p0>; nvmem-cell-names = "phy-cal-data"; leds { #address-cells = <1>; #size-cells = <0>; gsw_phy0_led0: led@0 { reg = <0>; status = "disabled"; }; gsw_phy0_led1: led@1 { reg = <1>; status = "disabled"; }; }; }; gsw_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; interrupts = <1>; nvmem-cells = <&phy_calibration_p1>; nvmem-cell-names = "phy-cal-data"; leds { #address-cells = <1>; #size-cells = <0>; gsw_phy1_led0: led@0 { reg = <0>; status = "disabled"; }; gsw_phy1_led1: led@1 { reg = <1>; status = "disabled"; }; }; }; gsw_phy2: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <2>; interrupts = <2>; nvmem-cells = <&phy_calibration_p2>; nvmem-cell-names = "phy-cal-data"; leds { #address-cells = <1>; #size-cells = <0>; gsw_phy2_led0: led@0 { reg = <0>; status = "disabled"; }; gsw_phy2_led1: led@1 { reg = <1>; status = "disabled"; }; }; }; gsw_phy3: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; interrupts = <3>; nvmem-cells = <&phy_calibration_p3>; nvmem-cell-names = "phy-cal-data"; leds { #address-cells = <1>; #size-cells = <0>; gsw_phy3_led0: led@0 { reg = <0>; status = "disabled"; }; gsw_phy3_led1: led@1 { reg = <1>; status = "disabled"; }; }; }; }; }; ethwarp: clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; eth: ethernet@15100000 { compatible = "mediatek,mt7988-eth"; reg = <0 0x15100000 0 0x40000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", "pdma1", "pdma2", "pdma3"; clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, <ðsys CLK_ETHDMA_FE_EN>, <ðsys CLK_ETHDMA_GP2_EN>, <ðsys CLK_ETHDMA_GP1_EN>, <ðsys CLK_ETHDMA_GP3_EN>, <ðwarp CLK_ETHWARP_WOCPU2_EN>, <ðwarp CLK_ETHWARP_WOCPU1_EN>, <ðwarp CLK_ETHWARP_WOCPU0_EN>, <ðsys CLK_ETHDMA_ESW_EN>, <&topckgen CLK_TOP_ETH_GMII_SEL>, <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, <&topckgen CLK_TOP_ETH_SYS_SEL>, <&topckgen CLK_TOP_ETH_XGMII_SEL>, <&topckgen CLK_TOP_ETH_MII_SEL>, <&topckgen CLK_TOP_NETSYS_SEL>, <&topckgen CLK_TOP_NETSYS_500M_SEL>, <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, <&topckgen CLK_TOP_NETSYS_WARP_SEL>, <ðsys CLK_ETHDMA_XGP1_EN>, <ðsys CLK_ETHDMA_XGP2_EN>, <ðsys CLK_ETHDMA_XGP3_EN>; clock-names = "crypto", "fe", "gp2", "gp1", "gp3", "ethwarp_wocpu2", "ethwarp_wocpu1", "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", "top_eth_sys_sel", "top_eth_xgmii_sel", "top_eth_mii_sel", "top_netsys_sel", "top_netsys_500m_sel", "top_netsys_pao_2x_sel", "top_netsys_sync_250m_sel", "top_netsys_ppefb_250m_sel", "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, <&topckgen CLK_TOP_NETSYS_GSW_SEL>, <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, <&topckgen CLK_TOP_SGM_0_SEL>, <&topckgen CLK_TOP_SGM_1_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, <&topckgen CLK_TOP_NET1PLL_D4>, <&topckgen CLK_TOP_NET1PLL_D8_D4>, <&topckgen CLK_TOP_NET1PLL_D8_D4>, <&apmixedsys CLK_APMIXED_SGMPLL>, <&apmixedsys CLK_APMIXED_SGMPLL>; sram = <ð_sram>; #address-cells = <1>; #size-cells = <0>; mediatek,ethsys = <ðsys>; mediatek,infracfg = <&topmisc>; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "internal"; /* Connected to internal switch */ fixed-link { speed = <10000>; full-duplex; pause; }; }; gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; status = "disabled"; }; gmac2: mac@2 { compatible = "mediatek,eth-mac"; reg = <2>; status = "disabled"; }; mdio_bus: mdio-bus { #address-cells = <1>; #size-cells = <0>; /* internal 2.5G PHY */ int_2p5g_phy: ethernet-phy@15 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <15>; status = "disabled"; }; }; }; eth_sram: sram@15400000 { compatible = "mmio-sram"; reg = <0 0x15400000 0 0x200000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x15400000 0 0x200000>; }; }; thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&lvts 0>; trips { cpu_trip_crit: crit { temperature = <125000>; hysteresis = <2000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; |