Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2023 MediaTek Inc. * */ /dts-v1/; #include <dt-bindings/clock/mediatek,mt8188-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/mailbox/mediatek,mt8188-gce.h> #include <dt-bindings/memory/mediatek,mt8188-memory-port.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> #include <dt-bindings/power/mediatek,mt8188-power.h> #include <dt-bindings/reset/mt8188-resets.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/mediatek,lvts-thermal.h> / { compatible = "mediatek,mt8188"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; dsc0 = &dsc0; ethdr0 = ðdr0; gce0 = &gce0; gce1 = &gce1; merge0 = &merge0; merge1 = &merge1; merge2 = &merge2; merge3 = &merge3; merge4 = &merge4; merge5 = &merge5; mutex0 = &mutex0; mutex1 = &mutex1; padding0 = &padding0; padding1 = &padding1; padding2 = &padding2; padding3 = &padding3; padding4 = &padding4; padding5 = &padding5; padding6 = &padding6; padding7 = &padding7; vdo1-rdma0 = &vdo1_rdma0; vdo1-rdma1 = &vdo1_rdma1; vdo1-rdma2 = &vdo1_rdma2; vdo1-rdma3 = &vdo1_rdma3; vdo1-rdma4 = &vdo1_rdma4; vdo1-rdma5 = &vdo1_rdma5; vdo1-rdma6 = &vdo1_rdma6; vdo1-rdma7 = &vdo1_rdma7; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x000>; enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <282>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; i-cache-size = <32768>; i-cache-line-size = <64>; i-cache-sets = <128>; d-cache-size = <32768>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; #cooling-cells = <2>; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <282>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; i-cache-size = <32768>; i-cache-line-size = <64>; i-cache-sets = <128>; d-cache-size = <32768>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; #cooling-cells = <2>; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x200>; enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <282>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; i-cache-size = <32768>; i-cache-line-size = <64>; i-cache-sets = <128>; d-cache-size = <32768>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; #cooling-cells = <2>; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x300>; enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <282>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; i-cache-size = <32768>; i-cache-line-size = <64>; i-cache-sets = <128>; d-cache-size = <32768>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; #cooling-cells = <2>; }; cpu4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x400>; enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <282>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; i-cache-size = <32768>; i-cache-line-size = <64>; i-cache-sets = <128>; d-cache-size = <32768>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; #cooling-cells = <2>; }; cpu5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x500>; enable-method = "psci"; clock-frequency = <2000000000>; capacity-dmips-mhz = <282>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; i-cache-size = <32768>; i-cache-line-size = <64>; i-cache-sets = <128>; d-cache-size = <32768>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; performance-domains = <&performance 0>; #cooling-cells = <2>; }; cpu6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x600>; enable-method = "psci"; clock-frequency = <2600000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; performance-domains = <&performance 1>; #cooling-cells = <2>; }; cpu7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x700>; enable-method = "psci"; clock-frequency = <2600000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; i-cache-size = <65536>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; performance-domains = <&performance 1>; #cooling-cells = <2>; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; core4 { cpu = <&cpu4>; }; core5 { cpu = <&cpu5>; }; core6 { cpu = <&cpu6>; }; core7 { cpu = <&cpu7>; }; }; }; idle-states { entry-method = "psci"; cpu_off_l: cpu-off-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010000>; local-timer-stop; entry-latency-us = <50>; exit-latency-us = <95>; min-residency-us = <580>; }; cpu_off_b: cpu-off-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x00010000>; local-timer-stop; entry-latency-us = <45>; exit-latency-us = <140>; min-residency-us = <740>; }; cluster_off_l: cluster-off-l { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010010>; local-timer-stop; entry-latency-us = <55>; exit-latency-us = <155>; min-residency-us = <840>; }; cluster_off_b: cluster-off-b { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x01010010>; local-timer-stop; entry-latency-us = <50>; exit-latency-us = <200>; min-residency-us = <1000>; }; }; l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; cache-unified; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; next-level-cache = <&l3_0>; cache-unified; }; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; cache-unified; }; }; clk13m: oscillator-13m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <13000000>; clock-output-names = "clk13m"; }; clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; clk32k: oscillator-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "clk32k"; }; gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; opp-shared; opp-390000000 { opp-hz = /bits/ 64 <390000000>; opp-microvolt = <575000>; opp-supported-hw = <0xff>; }; opp-431000000 { opp-hz = /bits/ 64 <431000000>; opp-microvolt = <587500>; opp-supported-hw = <0xff>; }; opp-473000000 { opp-hz = /bits/ 64 <473000000>; opp-microvolt = <600000>; opp-supported-hw = <0xff>; }; opp-515000000 { opp-hz = /bits/ 64 <515000000>; opp-microvolt = <612500>; opp-supported-hw = <0xff>; }; opp-556000000 { opp-hz = /bits/ 64 <556000000>; opp-microvolt = <625000>; opp-supported-hw = <0xff>; }; opp-598000000 { opp-hz = /bits/ 64 <598000000>; opp-microvolt = <637500>; opp-supported-hw = <0xff>; }; opp-640000000 { opp-hz = /bits/ 64 <640000000>; opp-microvolt = <650000>; opp-supported-hw = <0xff>; }; opp-670000000 { opp-hz = /bits/ 64 <670000000>; opp-microvolt = <662500>; opp-supported-hw = <0xff>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; opp-microvolt = <675000>; opp-supported-hw = <0xff>; }; opp-730000000 { opp-hz = /bits/ 64 <730000000>; opp-microvolt = <687500>; opp-supported-hw = <0xff>; }; opp-760000000 { opp-hz = /bits/ 64 <760000000>; opp-microvolt = <700000>; opp-supported-hw = <0xff>; }; opp-790000000 { opp-hz = /bits/ 64 <790000000>; opp-microvolt = <712500>; opp-supported-hw = <0xff>; }; opp-835000000 { opp-hz = /bits/ 64 <835000000>; opp-microvolt = <731250>; opp-supported-hw = <0xff>; }; opp-880000000 { opp-hz = /bits/ 64 <880000000>; opp-microvolt = <750000>; opp-supported-hw = <0xff>; }; opp-915000000 { opp-hz = /bits/ 64 <915000000>; opp-microvolt = <775000>; opp-supported-hw = <0x8f>; }; opp-915000000-5 { opp-hz = /bits/ 64 <915000000>; opp-microvolt = <762500>; opp-supported-hw = <0x30>; }; opp-915000000-6 { opp-hz = /bits/ 64 <915000000>; opp-microvolt = <750000>; opp-supported-hw = <0x70>; }; opp-950000000 { opp-hz = /bits/ 64 <950000000>; opp-microvolt = <800000>; opp-supported-hw = <0x8f>; }; opp-950000000-5 { opp-hz = /bits/ 64 <950000000>; opp-microvolt = <775000>; opp-supported-hw = <0x30>; }; opp-950000000-6 { opp-hz = /bits/ 64 <950000000>; opp-microvolt = <750000>; opp-supported-hw = <0x70>; }; }; pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; }; pmu-a78 { compatible = "arm,cortex-a78-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; sound: sound { mediatek,platform = <&afe>; status = "disabled"; }; thermal_zones: thermal-zones { cpu-little0-thermal { polling-delay = <1000>; polling-delay-passive = <150>; thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>; trips { cpu_little0_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_little0_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu_little0_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { cpu_little0_cooling_map0: map0 { trip = <&cpu_little0_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu-little1-thermal { polling-delay = <1000>; polling-delay-passive = <150>; thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>; trips { cpu_little1_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_little1_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu_little1_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { cpu_little1_cooling_map0: map0 { trip = <&cpu_little1_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu-little2-thermal { polling-delay = <1000>; polling-delay-passive = <150>; thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>; trips { cpu_little2_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_little2_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu_little2_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { cpu_little2_cooling_map0: map0 { trip = <&cpu_little2_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu-little3-thermal { polling-delay = <1000>; polling-delay-passive = <150>; thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>; trips { cpu_little3_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_little3_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu_little3_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { cpu_little3_cooling_map0: map0 { trip = <&cpu_little3_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu-big0-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>; trips { cpu_big0_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_big0_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu_big0_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_big0_alert0>; cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu-big1-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>; trips { cpu_big1_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cpu_big1_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu_big1_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_big1_alert0>; cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; apu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_APU>; trips { apu_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; apu_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; apu_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; }; gpu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_GPU0>; trips { gpu_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; gpu_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; gpu_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpu_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; gpu1-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_GPU1>; trips { gpu1_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; gpu1_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; gpu1_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpu1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; adsp-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_ADSP>; trips { soc_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; soc_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; soc_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; }; vdo-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_VDO>; trips { soc1_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; soc1_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; soc1_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; }; infra-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_INFRA>; trips { soc2_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; soc2_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; soc2_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; }; cam1-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_CAM1>; trips { cam1_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cam1_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cam1_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; }; cam2-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8188_AP_CAM2>; trips { cam2_alert0: trip-alert0 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; cam2_alert1: trip-alert1 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cam2_crit: trip-crit { temperature = <100000>; hysteresis = <0>; type = "critical"; }; }; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; clock-frequency = <13000000>; }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; ranges; performance: performance-controller@11bc10 { compatible = "mediatek,cpufreq-hw"; reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; #performance-domain-cells = <1>; }; gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; #redistributor-regions = <1>; interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x0c000000 0 0x40000>, <0 0x0c040000 0 0x200000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; ppi-partitions { ppi_cluster0: interrupt-partition-0 { affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; }; ppi_cluster1: interrupt-partition-1 { affinity = <&cpu6 &cpu7>; }; }; }; topckgen: syscon@10000000 { compatible = "mediatek,mt8188-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; }; infracfg_ao: syscon@10001000 { compatible = "mediatek,mt8188-infracfg-ao", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; pericfg: syscon@10003000 { compatible = "mediatek,mt8188-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; #clock-cells = <1>; }; pio: pinctrl@10005000 { compatible = "mediatek,mt8188-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x11c00000 0 0x1000>, <0 0x11e10000 0 0x1000>, <0 0x11e20000 0 0x1000>, <0 0x11ea0000 0 0x1000>, <0 0x1000b000 0 0x1000>; reg-names = "iocfg0", "iocfg_rm", "iocfg_lt", "iocfg_lm", "iocfg_rt", "eint"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 176>; interrupt-controller; interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; #interrupt-cells = <2>; }; scpsys: syscon@10006000 { compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; /* System Power Manager */ spm: power-controller { compatible = "mediatek,mt8188-power-controller"; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; /* power domain of the SoC */ mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { reg = <MT8188_POWER_DOMAIN_MFG0>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { reg = <MT8188_POWER_DOMAIN_MFG1>; clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, <&topckgen CLK_TOP_MFG_CORE_TMP>; clock-names = "mfg", "alt"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_MFG2 { reg = <MT8188_POWER_DOMAIN_MFG2>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_MFG3 { reg = <MT8188_POWER_DOMAIN_MFG3>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_MFG4 { reg = <MT8188_POWER_DOMAIN_MFG4>; #power-domain-cells = <0>; }; }; }; power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { reg = <MT8188_POWER_DOMAIN_VPPSYS0>; clocks = <&topckgen CLK_TOP_VPP>, <&topckgen CLK_TOP_CAM>, <&topckgen CLK_TOP_CCU>, <&topckgen CLK_TOP_IMG>, <&topckgen CLK_TOP_VENC>, <&topckgen CLK_TOP_VDEC>, <&topckgen CLK_TOP_WPE_VPP>, <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, <&vppsys0 CLK_VPP0_SMI_IOMMU>, <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, <&vppsys0 CLK_VPP0_SMI_RSI>, <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; clock-names = "top", "cam", "ccu", "img", "venc", "vdec", "wpe", "cfgck", "cfgxo", "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", "ss-sram-rdr", "ss-iommu", "ss-imgcam", "ss-emi", "ss-subcmn-rdr", "ss-rsi", "ss-cmn-l4", "ss-vdec1", "ss-wpe", "ss-cvdo-ve1"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { reg = <MT8188_POWER_DOMAIN_VDOSYS0>; clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, <&vdosys0 CLK_VDO0_SMI_GALS>, <&vdosys0 CLK_VDO0_SMI_COMMON>, <&vdosys0 CLK_VDO0_SMI_EMI>, <&vdosys0 CLK_VDO0_SMI_IOMMU>, <&vdosys0 CLK_VDO0_SMI_LARB>, <&vdosys0 CLK_VDO0_SMI_RSI>, <&vdosys0 CLK_VDO0_APB_BUS>; clock-names = "cfgck", "cfgxo", "ss-gals", "ss-cmn", "ss-emi", "ss-iommu", "ss-larb", "ss-rsi", "ss-bus"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { reg = <MT8188_POWER_DOMAIN_VPPSYS1>; clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, <&vppsys1 CLK_VPP1_GALS5>, <&vppsys1 CLK_VPP1_GALS6>, <&vppsys1 CLK_VPP1_LARB5>, <&vppsys1 CLK_VPP1_LARB6>; clock-names = "cfgck", "cfgxo", "ss-vpp1-g5", "ss-vpp1-g6", "ss-vpp1-l5", "ss-vpp1-l6"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_VDEC0 { reg = <MT8188_POWER_DOMAIN_VDEC0>; clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; clock-names = "ss-vdec1-soc-l1"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_VDEC1 { reg = <MT8188_POWER_DOMAIN_VDEC1>; clocks = <&vdecsys CLK_VDEC2_LARB1>; clock-names = "ss-vdec2-l1"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; }; cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { reg = <MT8188_POWER_DOMAIN_CAM_VCORE>; clocks = <&topckgen CLK_TOP_CAM>, <&topckgen CLK_TOP_CCU>, <&topckgen CLK_TOP_CCU_AHB>, <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; clock-names = "cam", "ccu", "bus", "cfgck"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { reg = <MT8188_POWER_DOMAIN_CAM_MAIN>; clocks = <&camsys CLK_CAM_MAIN_LARB13>, <&camsys CLK_CAM_MAIN_LARB14>, <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; clock-names= "ss-cam-l13", "ss-cam-l14", "ss-cam-mm0", "ss-cam-mm1", "ss-camsys"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { reg = <MT8188_POWER_DOMAIN_CAM_SUBB>; clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, <&camsys_rawb CLK_CAM_RAWB_LARBX>, <&camsys_yuvb CLK_CAM_YUVB_LARBX>; clock-names = "ss-camb-sub", "ss-camb-raw", "ss-camb-yuv"; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { reg =<MT8188_POWER_DOMAIN_CAM_SUBA>; clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, <&camsys_rawa CLK_CAM_RAWA_LARBX>, <&camsys_yuva CLK_CAM_YUVA_LARBX>; clock-names = "ss-cama-sub", "ss-cama-raw", "ss-cama-yuv"; #power-domain-cells = <0>; }; }; }; power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { reg = <MT8188_POWER_DOMAIN_VDOSYS1>; clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, <&vdosys1 CLK_VDO1_SMI_LARB2>, <&vdosys1 CLK_VDO1_SMI_LARB3>, <&vdosys1 CLK_VDO1_GALS>; clock-names = "cfgck", "cfgxo", "ss-larb2", "ss-larb3", "ss-gals"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_HDMI_TX { reg = <MT8188_POWER_DOMAIN_HDMI_TX>; clocks = <&topckgen CLK_TOP_HDMI_APB>, <&topckgen CLK_TOP_HDCP_24M>; clock-names = "bus", "hdcp"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_DP_TX { reg = <MT8188_POWER_DOMAIN_DP_TX>; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_EDP_TX { reg = <MT8188_POWER_DOMAIN_EDP_TX>; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; }; power-domain@MT8188_POWER_DOMAIN_VENC { reg = <MT8188_POWER_DOMAIN_VENC>; clocks = <&vencsys CLK_VENC1_LARB>, <&vencsys CLK_VENC1_VENC>, <&vencsys CLK_VENC1_GALS>, <&vencsys CLK_VENC1_GALS_SRAM>; clock-names = "ss-ve1-larb", "ss-ve1-core", "ss-ve1-gals", "ss-ve1-sram"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_WPE { reg = <MT8188_POWER_DOMAIN_WPE>; clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; }; }; power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; mediatek,infracfg = <&infracfg_ao>; clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; clock-names = "ss-pextp-fmem"; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>; clocks = <&topckgen CLK_TOP_SENINF>, <&topckgen CLK_TOP_SENINF1>; clock-names = "seninf0", "seninf1"; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_ADSP_AO { reg = <MT8188_POWER_DOMAIN_ADSP_AO>; clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, <&topckgen CLK_TOP_ADSP>; clock-names = "bus", "main"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>; clocks = <&topckgen CLK_TOP_ASM_H>; clock-names = "asm"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_AUDIO { reg = <MT8188_POWER_DOMAIN_AUDIO>; clocks = <&topckgen CLK_TOP_A1SYS_HP>, <&topckgen CLK_TOP_AUD_INTBUS>, <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; clock-names = "a1sys", "intbus", "adspck"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; power-domain@MT8188_POWER_DOMAIN_ADSP { reg = <MT8188_POWER_DOMAIN_ADSP>; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; }; }; power-domain@MT8188_POWER_DOMAIN_ETHER { reg = <MT8188_POWER_DOMAIN_ETHER>; clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; clock-names = "ethermac"; mediatek,infracfg = <&infracfg_ao>; #power-domain-cells = <0>; }; }; }; watchdog: watchdog@10007000 { compatible = "mediatek,mt8188-wdt"; reg = <0 0x10007000 0 0x100>; mediatek,disable-extrst; #reset-cells = <1>; }; apmixedsys: syscon@1000c000 { compatible = "mediatek,mt8188-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; #clock-cells = <1>; }; systimer: timer@10017000 { compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&clk13m>; }; pwrap: pwrap@10024000 { compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon"; reg = <0 0x10024000 0 0x1000>; reg-names = "pwrap"; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; clock-names = "spi", "wrap"; }; spmi: spmi@10027000 { compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi"; reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>; reg-names = "pmif", "spmimst"; assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>; assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, <&topckgen CLK_TOP_SPMI_M_MST>; clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; }; infra_iommu: iommu@10315000 { compatible = "mediatek,mt8188-iommu-infra"; reg = <0 0x10315000 0 0x1000>; interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>; #iommu-cells = <1>; }; gce0: mailbox@10320000 { compatible = "mediatek,mt8188-gce"; reg = <0 0x10320000 0 0x4000>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; #mbox-cells = <2>; clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; }; gce1: mailbox@10330000 { compatible = "mediatek,mt8188-gce"; reg = <0 0x10330000 0 0x4000>; interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; #mbox-cells = <2>; clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; }; scp_cluster: scp@10720000 { compatible = "mediatek,mt8188-scp-dual"; reg = <0 0x10720000 0 0xe0000>; reg-names = "cfg"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x10500000 0x100000>; status = "disabled"; scp_c0: scp@0 { compatible = "mediatek,scp-core"; reg = <0x0 0xd0000>; reg-names = "sram"; interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; scp_c1: scp@d0000 { compatible = "mediatek,scp-core"; reg = <0xd0000 0x2f000>; reg-names = "sram"; interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; status = "disabled"; }; }; afe: audio-controller@10b10000 { compatible = "mediatek,mt8188-afe"; reg = <0 0x10b10000 0 0x10000>; assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>; clocks = <&clk26m>, <&apmixedsys CLK_APMIXED_APLL1>, <&apmixedsys CLK_APMIXED_APLL2>, <&topckgen CLK_TOP_APLL12_CK_DIV0>, <&topckgen CLK_TOP_APLL12_CK_DIV1>, <&topckgen CLK_TOP_APLL12_CK_DIV2>, <&topckgen CLK_TOP_APLL12_CK_DIV3>, <&topckgen CLK_TOP_APLL12_CK_DIV9>, <&topckgen CLK_TOP_A1SYS_HP>, <&topckgen CLK_TOP_AUD_INTBUS>, <&topckgen CLK_TOP_AUDIO_H>, <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, <&topckgen CLK_TOP_DPTX>, <&topckgen CLK_TOP_I2SO1>, <&topckgen CLK_TOP_I2SO2>, <&topckgen CLK_TOP_I2SI1>, <&topckgen CLK_TOP_I2SI2>, <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>, <&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL12_CK_DIV4>, <&topckgen CLK_TOP_A2SYS>, <&topckgen CLK_TOP_AUD_IEC>; clock-names = "clk26m", "apll1", "apll2", "apll12_div0", "apll12_div1", "apll12_div2", "apll12_div3", "apll12_div9", "top_a1sys_hp", "top_aud_intbus", "top_audio_h", "top_audio_local_bus", "top_dptx", "top_i2so1", "top_i2so2", "top_i2si1", "top_i2si2", "adsp_audio_26m", "apll1_d4", "apll2_d4", "apll12_div4", "top_a2sys", "top_aud_iec"; interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>; resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>; reset-names = "audiosys"; mediatek,infracfg = <&infracfg_ao>; mediatek,topckgen = <&topckgen>; status = "disabled"; }; adsp: adsp@10b80000 { compatible = "mediatek,mt8188-dsp"; reg = <0 0x10b80000 0 0x2000>, <0 0x10d00000 0 0x80000>, <0 0x10b8b000 0 0x100>, <0 0x10b8f000 0 0x1000>; reg-names = "cfg", "sram", "sec", "bus"; assigned-clocks = <&topckgen CLK_TOP_ADSP>; clocks = <&topckgen CLK_TOP_ADSP>, <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; clock-names = "audiodsp", "adsp_bus"; mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; mbox-names = "rx", "tx"; power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>; status = "disabled"; }; adsp_mailbox0: mailbox@10b86100 { compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; reg = <0 0x10b86100 0 0x1000>; interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>; #mbox-cells = <0>; }; adsp_mailbox1: mailbox@10b87100 { compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; reg = <0 0x10b87100 0 0x1000>; interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>; #mbox-cells = <0>; }; adsp_audio26m: clock-controller@10b91100 { compatible = "mediatek,mt8188-adsp-audio26m"; reg = <0 0x10b91100 0 0x100>; #clock-cells = <1>; }; uart0: serial@11001100 { compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; reg = <0 0x11001100 0 0x100>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; clock-names = "baud", "bus"; status = "disabled"; }; uart1: serial@11001200 { compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; reg = <0 0x11001200 0 0x100>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; clock-names = "baud", "bus"; status = "disabled"; }; uart2: serial@11001300 { compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; reg = <0 0x11001300 0 0x100>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; clock-names = "baud", "bus"; status = "disabled"; }; uart3: serial@11001400 { compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart"; reg = <0 0x11001400 0 0x100>; interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; clock-names = "baud", "bus"; status = "disabled"; }; auxadc: adc@11002000 { compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; reg = <0 0x11002000 0 0x1000>; clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; clock-names = "main"; #io-channel-cells = <1>; status = "disabled"; }; pericfg_ao: syscon@11003000 { compatible = "mediatek,mt8188-pericfg-ao", "syscon"; reg = <0 0x11003000 0 0x1000>; #clock-cells = <1>; }; spi0: spi@1100a000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x1100a000 0 0x1000>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, <&topckgen CLK_TOP_SPI>, <&infracfg_ao CLK_INFRA_AO_SPI0>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; lvts_ap: thermal-sensor@1100b000 { compatible = "mediatek,mt8188-lvts-ap"; reg = <0 0x1100b000 0 0xc00>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>; nvmem-cells = <&lvts_efuse_data1>; nvmem-cell-names = "lvts-calib-data-1"; #thermal-sensor-cells = <1>; }; disp_pwm0: pwm@1100e000 { compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; clocks = <&topckgen CLK_TOP_DISP_PWM0>, <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; clock-names = "main", "mm"; interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; #pwm-cells = <2>; status = "disabled"; }; disp_pwm1: pwm@1100f000 { compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100f000 0 0x1000>; clocks = <&topckgen CLK_TOP_DISP_PWM1>, <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; clock-names = "main", "mm"; interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; #pwm-cells = <2>; status = "disabled"; }; spi1: spi@11010000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x11010000 0 0x1000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, <&topckgen CLK_TOP_SPI>, <&infracfg_ao CLK_INFRA_AO_SPI1>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; spi2: spi@11012000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x11012000 0 0x1000>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, <&topckgen CLK_TOP_SPI>, <&infracfg_ao CLK_INFRA_AO_SPI2>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; spi3: spi@11013000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x11013000 0 0x1000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, <&topckgen CLK_TOP_SPI>, <&infracfg_ao CLK_INFRA_AO_SPI3>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; spi4: spi@11018000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x11018000 0 0x1000>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, <&topckgen CLK_TOP_SPI>, <&infracfg_ao CLK_INFRA_AO_SPI4>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; spi5: spi@11019000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x11019000 0 0x1000>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, <&topckgen CLK_TOP_SPI>, <&infracfg_ao CLK_INFRA_AO_SPI5>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; ssusb1: usb@11201000 { compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; ranges = <0 0 0 0x11200000 0 0x3f00>; #address-cells = <2>; #size-cells = <2>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&topckgen CLK_TOP_USB_TOP>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, <&topckgen CLK_TOP_SSUSB_TOP_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; wakeup-source; mediatek,syscon-wakeup = <&pericfg 0x468 2>; status = "disabled"; xhci1: usb@0 { compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; reg = <0 0 0 0x1000>; reg-names = "mac"; interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; clock-names = "sys_ck"; status = "disabled"; }; }; eth: ethernet@11021000 { compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; reg = <0 0x11021000 0 0x4000>; interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "macirq"; clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, <&topckgen CLK_TOP_SNPS_ETH_250M>, <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; clock-names = "axi", "apb", "mac_main", "ptp_ref", "rmii_internal", "mac_cg"; assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, <&topckgen CLK_TOP_ETHPLL_D8>, <&topckgen CLK_TOP_ETHPLL_D10>; power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>; mediatek,pericfg = <&infracfg_ao>; snps,axi-config = <&stmmac_axi_setup>; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; snps,txpbl = <16>; snps,rxpbl = <16>; snps,clk-csr = <0>; status = "disabled"; eth_mdio: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; stmmac_axi_setup: stmmac-axi-config { snps,blen = <0 0 0 0 16 8 4>; snps,rd_osr_lmt = <0x7>; snps,wr_osr_lmt = <0x7>; }; mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <4>; snps,rx-sched-sp; queue0 { snps,dcb-algorithm; snps,map-to-dma-channel = <0x0>; }; queue1 { snps,dcb-algorithm; snps,map-to-dma-channel = <0x0>; }; queue2 { snps,dcb-algorithm; snps,map-to-dma-channel = <0x0>; }; queue3 { snps,dcb-algorithm; snps,map-to-dma-channel = <0x0>; }; }; mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <4>; snps,tx-sched-wrr; queue0 { snps,dcb-algorithm; snps,priority = <0x0>; snps,weight = <0x10>; }; queue1 { snps,dcb-algorithm; snps,priority = <0x1>; snps,weight = <0x11>; }; queue2 { snps,dcb-algorithm; snps,priority = <0x2>; snps,weight = <0x12>; }; queue3 { snps,dcb-algorithm; snps,priority = <0x3>; snps,weight = <0x13>; }; }; }; mmc0: mmc@11230000 { compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11230000 0 0x10000>, <0 0x11f50000 0 0x1000>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC50_0>, <&infracfg_ao CLK_INFRA_AO_MSDC0>, <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; clock-names = "source", "hclk", "source_cg", "crypto_clk"; status = "disabled"; }; mmc1: mmc@11240000 { compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11240000 0 0x1000>, <0 0x11eb0000 0 0x1000>; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_1>, <&infracfg_ao CLK_INFRA_AO_MSDC1>, <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; clock-names = "source", "hclk", "source_cg"; assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; status = "disabled"; }; mmc2: mmc@11250000 { compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11250000 0 0x1000>, <0 0x11e60000 0 0x1000>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_2>, <&infracfg_ao CLK_INFRA_AO_MSDC2>, <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; clock-names = "source", "hclk", "source_cg"; assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; status = "disabled"; }; lvts_mcu: thermal-sensor@11278000 { compatible = "mediatek,mt8188-lvts-mcu"; reg = <0 0x11278000 0 0x1000>; interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>; nvmem-cells = <&lvts_efuse_data1>; nvmem-cell-names = "lvts-calib-data-1"; #thermal-sensor-cells = <1>; }; i2c0: i2c@11280000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11280000 0 0x1000>, <0 0x10220080 0 0x80>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; clock-div = <1>; clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@11281000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11281000 0 0x1000>, <0 0x10220180 0 0x80>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; clock-div = <1>; clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@11282000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11282000 0 0x1000>, <0 0x10220280 0 0x80>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; clock-div = <1>; clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; imp_iic_wrap_c: clock-controller@11283000 { compatible = "mediatek,mt8188-imp-iic-wrap-c"; reg = <0 0x11283000 0 0x1000>; #clock-cells = <1>; }; ssusb2: usb@112a1000 { compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; reg-names = "mac", "ippc"; ranges = <0 0 0 0x112a0000 0 0x3f00>; #address-cells = <2>; #size-cells = <2>; interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; phys = <&u2port2 PHY_TYPE_USB2>; wakeup-source; mediatek,syscon-wakeup = <&pericfg 0x470 2>; status = "disabled"; xhci2: usb@0 { compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; reg = <0 0 0 0x1000>; reg-names = "mac"; interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; clock-names = "sys_ck"; status = "disabled"; }; }; ssusb0: usb@112b1000 { compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; reg-names = "mac", "ippc"; ranges = <0 0 0 0x112b0000 0 0x3f00>; #address-cells = <2>; #size-cells = <2>; interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; phys = <&u2port0 PHY_TYPE_USB2>; wakeup-source; mediatek,syscon-wakeup = <&pericfg 0x460 2>; status = "disabled"; xhci0: usb@0 { compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; reg = <0 0 0 0x1000>; reg-names = "mac"; interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; clock-names = "sys_ck"; status = "disabled"; }; }; pcie: pcie@112f0000 { compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; reg = <0 0x112f0000 0 0x2000>; reg-names = "pcie-mac"; ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; bus-range = <0 0xff>; device_type = "pci"; linux,pci-domain = <0>; #address-cells = <3>; #size-cells = <2>; clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", "peri_26m", "peri_mem"; #interrupt-cells = <1>; interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; iommu-map-mask = <0>; phys = <&pcieport PHY_TYPE_PCIE>; phy-names = "pcie-phy"; power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; reset-names = "mac"; status = "disabled"; pcie_intc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; nor_flash: spi@1132c000 { compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; reg = <0 0x1132c000 0 0x1000>; clocks = <&topckgen CLK_TOP_SPINOR>, <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; clock-names = "spi", "sf", "axi"; assigned-clocks = <&topckgen CLK_TOP_SPINOR>; interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; pciephy: t-phy@11c20700 { compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; ranges = <0 0 0x11c20700 0x700>; #address-cells = <1>; #size-cells = <1>; power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; status = "disabled"; pcieport: pcie-phy@0 { reg = <0 0x700>; clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; clock-names = "ref"; #phy-cells = <1>; }; }; mipi_tx_config0: dsi-phy@11c80000 { compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; reg = <0 0x11c80000 0 0x1000>; clocks = <&clk26m>; clock-output-names = "mipi_tx0_pll"; #clock-cells = <0>; #phy-cells = <0>; status = "disabled"; }; mipi_tx_config1: dsi-phy@11c90000 { compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; reg = <0 0x11c90000 0 0x1000>; clocks = <&clk26m>; clock-output-names = "mipi_tx0_pll"; #clock-cells = <0>; #phy-cells = <0>; status = "disabled"; }; i2c1: i2c@11e00000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11e00000 0 0x1000>, <0 0x10220100 0 0x80>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; clock-div = <1>; clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@11e01000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11e01000 0 0x1000>, <0 0x10220380 0 0x80>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; clock-div = <1>; clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; imp_iic_wrap_w: clock-controller@11e02000 { compatible = "mediatek,mt8188-imp-iic-wrap-w"; reg = <0 0x11e02000 0 0x1000>; #clock-cells = <1>; }; u3phy0: t-phy@11e30000 { compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x11e30000 0x1000>; status = "disabled"; u2port0: usb-phy@0 { reg = <0x0 0x700>; clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; clock-names = "ref", "da_ref"; #phy-cells = <1>; }; }; u3phy1: t-phy@11e40000 { compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x11e40000 0x1000>; status = "disabled"; u2port1: usb-phy@0 { reg = <0x0 0x700>; clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; clock-names = "ref", "da_ref"; #phy-cells = <1>; }; u3port1: usb-phy@700 { reg = <0x700 0x700>; clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, <&clk26m>; clock-names = "ref", "da_ref"; #phy-cells = <1>; }; }; u3phy2: t-phy@11e80000 { compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x11e80000 0x1000>; status = "disabled"; u2port2: usb-phy@0 { reg = <0x0 0x700>; clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; clock-names = "ref", "da_ref"; #phy-cells = <1>; }; }; i2c5: i2c@11ec0000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11ec0000 0 0x1000>, <0 0x10220480 0 0x80>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; clock-div = <1>; clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c6: i2c@11ec1000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11ec1000 0 0x1000>, <0 0x10220600 0 0x80>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; clock-div = <1>; clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; imp_iic_wrap_en: clock-controller@11ec2000 { compatible = "mediatek,mt8188-imp-iic-wrap-en"; reg = <0 0x11ec2000 0 0x1000>; #clock-cells = <1>; }; efuse: efuse@11f20000 { compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse"; reg = <0 0x11f20000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; dp_calib_data: dp-calib@1a0 { reg = <0x1a0 0xc>; }; lvts_efuse_data1: lvts1-calib@1ac { reg = <0x1ac 0x40>; }; gpu_speedbin: gpu-speedbin@581 { reg = <0x581 0x1>; bits = <0 3>; }; socinfo-data1@7a0 { reg = <0x7a0 0x4>; }; socinfo-data2@7e0 { reg = <0x7e0 0x4>; }; }; gpu: gpu@13000000 { compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; reg = <0 0x13000000 0 0x4000>; clocks = <&mfgcfg CLK_MFGCFG_BG3D>; interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>, <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "job", "mmu", "gpu"; nvmem-cells = <&gpu_speedbin>; nvmem-cell-names = "speed-bin"; operating-points-v2 = <&gpu_opp_table>; power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, <&spm MT8188_POWER_DOMAIN_MFG3>, <&spm MT8188_POWER_DOMAIN_MFG4>; power-domain-names = "core0", "core1", "core2"; #cooling-cells = <2>; status = "disabled"; }; mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8188-mfgcfg"; reg = <0 0x13fbf000 0 0x1000>; #clock-cells = <1>; }; vppsys0: syscon@14000000 { compatible = "mediatek,mt8188-vppsys0", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; dma-controller@14001000 { compatible = "mediatek,mt8188-mdp3-rdma"; reg = <0 0x14001000 0 0x1000>; #dma-cells = <1>; clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; mboxes = <&gce0 13 CMDQ_THR_PRIO_1>, <&gce0 14 CMDQ_THR_PRIO_1>, <&gce0 16 CMDQ_THR_PRIO_1>, <&gce0 21 CMDQ_THR_PRIO_1>, <&gce0 22 CMDQ_THR_PRIO_1>; iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; mediatek,scp = <&scp_c0>; }; display@14002000 { compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; reg = <0 0x14002000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_FG>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; }; display@14004000 { compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; reg = <0 0x14004000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; }; display@14005000 { compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; reg = <0 0x14005000 0 0x1000>; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; }; display@14006000 { compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; reg = <0 0x14006000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; }; display@14007000 { compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; reg = <0 0x14007000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; }; display@14008000 { compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; reg = <0 0x14008000 0 0x1000>; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; }; display@14009000 { compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl"; reg = <0 0x14009000 0 0x1000>; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>; }; display@1400a000 { compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding"; reg = <0 0x1400a000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_PADDING>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; }; display@1400b000 { compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc"; reg = <0 0x1400b000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; }; display@1400c000 { compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; reg = <0 0x1400c000 0 0x1000>; #dma-cells = <1>; clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; }; mutex@1400f000 { compatible = "mediatek,mt8188-vpp-mutex"; reg = <0 0x1400f000 0 0x1000>; interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys0 CLK_VPP0_MUTEX>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; }; vpp_smi_common: smi@14012000 { compatible = "mediatek,mt8188-smi-common-vpp"; reg = <0 0x14012000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; }; larb4: smi@14013000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x14013000 0 0x1000>; clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; mediatek,larb-id = <SMI_L4_ID>; mediatek,smi = <&vpp_smi_common>; }; vpp_iommu: iommu@14018000 { compatible = "mediatek,mt8188-iommu-vpp"; reg = <0 0x14018000 0 0x5000>; clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; clock-names = "bclk"; interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; #iommu-cells = <1>; mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>; }; dma-controller@14f09000 { compatible = "mediatek,mt8188-mdp3-rdma"; reg = <0 0x14f09000 0 0x1000>; #dma-cells = <1>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; }; dma-controller@14f0a000 { compatible = "mediatek,mt8188-mdp3-rdma"; reg = <0 0x14f0a000 0 0x1000>; #dma-cells = <1>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; }; display@14f0c000 { compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; reg = <0 0x14f0c000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; }; display@14f0d000 { compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg"; reg = <0 0x14f0d000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; }; display@14f0f000 { compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; reg = <0 0x14f0f000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; }; display@14f10000 { compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr"; reg = <0 0x14f10000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; }; display@14f12000 { compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; reg = <0 0x14f12000 0 0x1000>; interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; }; display@14f13000 { compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal"; reg = <0 0x14f13000 0 0x1000>; interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; }; display@14f15000 { compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; reg = <0 0x14f15000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; }; display@14f16000 { compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; reg = <0 0x14f16000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; }; display@14f18000 { compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; reg = <0 0x14f18000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; }; display@14f19000 { compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp"; reg = <0 0x14f19000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; }; display@14f1a000 { compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; reg = <0 0x14f1a000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; }; display@14f1b000 { compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge"; reg = <0 0x14f1b000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; }; display@14f1d000 { compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; reg = <0 0x14f1d000 0 0x1000>; interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; }; display@14f1e000 { compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color"; reg = <0 0x14f1e000 0 0x1000>; interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; }; display@14f21000 { compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding"; reg = <0 0x14f21000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; }; display@14f22000 { compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding"; reg = <0 0x14f22000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; }; display@14f24000 { compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; reg = <0 0x14f24000 0 0x1000>; #dma-cells = <1>; clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; }; display@14f25000 { compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; reg = <0 0x14f25000 0 0x1000>; #dma-cells = <1>; clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; }; wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8188-wpesys"; reg = <0 0x14e00000 0 0x1000>; #clock-cells = <1>; }; wpesys_vpp0: clock-controller@14e02000 { compatible = "mediatek,mt8188-wpesys-vpp0"; reg = <0 0x14e02000 0 0x1000>; #clock-cells = <1>; }; larb7: smi@14e04000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x14e04000 0 0x1000>; clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, <&wpesys CLK_WPE_TOP_SMI_LARB7>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_WPE>; mediatek,larb-id = <SMI_L7_ID>; mediatek,smi = <&vpp_smi_common>; }; vppsys1: syscon@14f00000 { compatible = "mediatek,mt8188-vppsys1", "syscon"; reg = <0 0x14f00000 0 0x1000>; #clock-cells = <1>; }; mutex@14f01000 { compatible = "mediatek,mt8188-vpp-mutex"; reg = <0 0x14f01000 0 0x1000>; interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; }; larb5: smi@14f02000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x14f02000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_GALS5>, <&vppsys1 CLK_VPP1_LARB5>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,larb-id = <SMI_L5_ID>; mediatek,smi = <&vdo_smi_common>; }; larb6: smi@14f03000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x14f03000 0 0x1000>; clocks = <&vppsys1 CLK_VPP1_GALS6>, <&vppsys1 CLK_VPP1_LARB6>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; mediatek,larb-id = <SMI_L6_ID>; mediatek,smi = <&vpp_smi_common>; }; imgsys: clock-controller@15000000 { compatible = "mediatek,mt8188-imgsys"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; imgsys1_dip_top: clock-controller@15110000 { compatible = "mediatek,mt8188-imgsys1-dip-top"; reg = <0 0x15110000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; imgsys1_dip_nr: clock-controller@15130000 { compatible = "mediatek,mt8188-imgsys1-dip-nr"; reg = <0 0x15130000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; imgsys_wpe1: clock-controller@15220000 { compatible = "mediatek,mt8188-imgsys-wpe1"; reg = <0 0x15220000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; ipesys: clock-controller@15330000 { compatible = "mediatek,mt8188-ipesys"; reg = <0 0x15330000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; imgsys_wpe2: clock-controller@15520000 { compatible = "mediatek,mt8188-imgsys-wpe2"; reg = <0 0x15520000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; imgsys_wpe3: clock-controller@15620000 { compatible = "mediatek,mt8188-imgsys-wpe3"; reg = <0 0x15620000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; camsys: clock-controller@16000000 { compatible = "mediatek,mt8188-camsys"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; camsys_rawa: clock-controller@1604f000 { compatible = "mediatek,mt8188-camsys-rawa"; reg = <0 0x1604f000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; camsys_yuva: clock-controller@1606f000 { compatible = "mediatek,mt8188-camsys-yuva"; reg = <0 0x1606f000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; camsys_rawb: clock-controller@1608f000 { compatible = "mediatek,mt8188-camsys-rawb"; reg = <0 0x1608f000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; camsys_yuvb: clock-controller@160af000 { compatible = "mediatek,mt8188-camsys-yuvb"; reg = <0 0x160af000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; ccusys: clock-controller@17200000 { compatible = "mediatek,mt8188-ccusys"; reg = <0 0x17200000 0 0x1000>; #clock-cells = <1>; }; video_decoder: video-decoder@18000000 { compatible = "mediatek,mt8188-vcodec-dec"; reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; ranges = <0 0 0 0x18000000 0 0x26000>; iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; #address-cells = <2>; #size-cells = <2>; mediatek,scp = <&scp_c0>; video-codec@10000 { compatible = "mediatek,mtk-vcodec-lat"; reg = <0 0x10000 0 0x800>; assigned-clocks = <&topckgen CLK_TOP_VDEC>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; clocks = <&topckgen CLK_TOP_VDEC>, <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, <&vdecsys_soc CLK_VDEC1_SOC_LAT>, <&topckgen CLK_TOP_UNIVPLL_D6>; clock-names = "sel", "vdec", "lat", "top"; interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; }; video-codec@25000 { compatible = "mediatek,mtk-vcodec-core"; reg = <0 0x25000 0 0x1000>; assigned-clocks = <&topckgen CLK_TOP_VDEC>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; clocks = <&topckgen CLK_TOP_VDEC>, <&vdecsys CLK_VDEC2_VDEC>, <&vdecsys CLK_VDEC2_LAT>, <&topckgen CLK_TOP_UNIVPLL_D6>; clock-names = "sel", "vdec", "lat", "top"; interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; }; }; larb23: smi@1800d000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1800d000 0 0x1000>; clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>, <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; mediatek,larb-id = <SMI_L23_ID>; mediatek,smi = <&vpp_smi_common>; }; vdecsys_soc: clock-controller@1800f000 { compatible = "mediatek,mt8188-vdecsys-soc"; reg = <0 0x1800f000 0 0x1000>; #clock-cells = <1>; }; larb21: smi@1802e000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1802e000 0 0x1000>; clocks = <&vdecsys CLK_VDEC2_LARB1>, <&vdecsys CLK_VDEC2_LARB1>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; mediatek,larb-id = <SMI_L21_ID>; mediatek,smi = <&vdo_smi_common>; }; vdecsys: clock-controller@1802f000 { compatible = "mediatek,mt8188-vdecsys"; reg = <0 0x1802f000 0 0x1000>; #clock-cells = <1>; }; vencsys: clock-controller@1a000000 { compatible = "mediatek,mt8188-vencsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; larb19: smi@1a010000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1a010000 0 0x1000>; clocks = <&vencsys CLK_VENC1_VENC>, <&vencsys CLK_VENC1_VENC>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; mediatek,larb-id = <SMI_L19_ID>; mediatek,smi = <&vdo_smi_common>; }; video_encoder: video-encoder@1a020000 { compatible = "mediatek,mt8188-vcodec-enc"; reg = <0 0x1a020000 0 0x10000>; #address-cells = <2>; #size-cells = <2>; assigned-clocks = <&topckgen CLK_TOP_VENC>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; clocks = <&vencsys CLK_VENC1_VENC>; clock-names = "venc_sel"; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, <&vdo_iommu M4U_PORT_L19_VENC_REC>, <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; mediatek,scp = <&scp_c0>; }; jpeg_encoder: jpeg-encoder@1a030000 { compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; reg = <0 0x1a030000 0 0x10000>; clocks = <&vencsys CLK_VENC1_JPGENC>; clock-names = "jpgenc"; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; }; jpeg_decoder: jpeg-decoder@1a040000 { compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; reg = <0 0x1a040000 0 0x10000>; clocks = <&vencsys CLK_VENC1_LARB>, <&vencsys CLK_VENC1_JPGDEC>; clock-names = "jpgdec-smi", "jpgdec"; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>, <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>, <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>, <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>, <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>, <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; }; ovl0: ovl@1c000000 { compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl"; reg = <0 0x1c000000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; ovl0_in: endpoint { }; }; port@1 { reg = <1>; ovl0_out: endpoint { remote-endpoint = <&rdma0_in>; }; }; }; }; rdma0: rdma@1c002000 { compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; reg = <0 0x1c002000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vpp_iommu M4U_PORT_L1_DISP_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; rdma0_in: endpoint { remote-endpoint = <&ovl0_out>; }; }; port@1 { reg = <1>; rdma0_out: endpoint { remote-endpoint = <&color0_in>; }; }; }; }; color0: color@1c003000 { compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color"; reg = <0 0x1c003000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; color0_in: endpoint { remote-endpoint = <&rdma0_out>; }; }; port@1 { reg = <1>; color0_out: endpoint { remote-endpoint = <&ccorr0_in>; }; }; }; }; ccorr0: ccorr@1c004000 { compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr"; reg = <0 0x1c004000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; ccorr0_in: endpoint { remote-endpoint = <&color0_out>; }; }; port@1 { reg = <1>; ccorr0_out: endpoint { remote-endpoint = <&aal0_in>; }; }; }; }; aal0: aal@1c005000 { compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; reg = <0 0x1c005000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; aal0_in: endpoint { remote-endpoint = <&ccorr0_out>; }; }; port@1 { reg = <1>; aal0_out: endpoint { remote-endpoint = <&gamma0_in>; }; }; }; }; gamma0: gamma@1c006000 { compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma"; reg = <0 0x1c006000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; gamma0_in: endpoint { remote-endpoint = <&aal0_out>; }; }; port@1 { reg = <1>; gamma0_out: endpoint { }; }; }; }; dither0: dither@1c007000 { compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither"; reg = <0 0x1c007000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dither0_in: endpoint { }; }; port@1 { reg = <1>; dither0_out: endpoint { }; }; }; }; disp_dsi0: dsi@1c008000 { compatible = "mediatek,mt8188-dsi"; reg = <0 0x1c008000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DSI0>, <&vdosys0 CLK_VDO0_DSI0_DSI>, <&mipi_tx_config0>; clock-names = "engine", "digital", "hs"; interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&mipi_tx_config0>; phy-names = "dphy"; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; resets = <&vdosys0 MT8188_VDO0_RST_DSI0>; status = "disabled"; }; dsc0: dsc@1c009000 { compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc"; reg = <0 0x1c009000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; }; disp_dsi1: dsi@1c012000 { compatible = "mediatek,mt8188-dsi"; reg = <0 0x1c012000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DSI1>, <&vdosys0 CLK_VDO0_DSI1_DSI>, <&mipi_tx_config1>; clock-names = "engine", "digital", "hs"; interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; phys = <&mipi_tx_config1>; phy-names = "dphy"; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; resets = <&vdosys0 MT8188_VDO0_RST_DSI1>; status = "disabled"; }; merge0: merge0@1c014000 { compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; reg = <0 0x1c014000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>, <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>; clock-names = "merge", "merge_async"; interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; dp_intf0: dp-intf@1c015000 { compatible = "mediatek,mt8188-dp-intf"; reg = <0 0x1c015000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, <&vdosys0 CLK_VDO0_DP_INTF0>, <&apmixedsys CLK_APMIXED_TVDPLL1>; clock-names = "pixel", "engine", "pll"; interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; status = "disabled"; }; mutex0: mutex@1c016000 { compatible = "mediatek,mt8188-disp-mutex"; reg = <0 0x1c016000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; }; postmask0: postmask@1c01a000 { compatible = "mediatek,mt8188-disp-postmask", "mediatek,mt8192-disp-postmask"; reg = <0 0x1c01a000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; postmask0_in: endpoint { }; }; port@1 { reg = <1>; postmask0_out: endpoint { }; }; }; }; vdosys0: syscon@1c01d000 { compatible = "mediatek,mt8188-vdosys0", "syscon"; reg = <0 0x1c01d000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; }; larb0: smi@1c022000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1c022000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, <&vdosys0 CLK_VDO0_SMI_LARB>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,larb-id = <SMI_L0_ID>; mediatek,smi = <&vdo_smi_common>; }; larb1: smi@1c023000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1c023000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, <&vdosys0 CLK_VDO0_SMI_LARB>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,larb-id = <SMI_L1_ID>; mediatek,smi = <&vpp_smi_common>; }; vdo_smi_common: smi@1c024000 { compatible = "mediatek,mt8188-smi-common-vdo"; reg = <0 0x1c024000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, <&vdosys0 CLK_VDO0_SMI_GALS>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; }; vdo_iommu: iommu@1c028000 { compatible = "mediatek,mt8188-iommu-vdo"; reg = <0 0x1c028000 0 0x5000>; clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; clock-names = "bclk"; interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; #iommu-cells = <1>; mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>; }; vdosys1: syscon@1c100000 { compatible = "mediatek,mt8188-vdosys1", "syscon"; reg = <0 0x1c100000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; }; mutex1: mutex@1c101000 { compatible = "mediatek,mt8188-disp-mutex"; reg = <0 0x1c101000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; }; larb2: smi@1c102000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1c102000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, <&vdosys1 CLK_VDO1_SMI_LARB2>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,larb-id = <SMI_L2_ID>; mediatek,smi = <&vdo_smi_common>; }; larb3: smi@1c103000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1c103000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, <&vdosys1 CLK_VDO1_SMI_LARB3>; clock-names = "apb", "smi"; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,larb-id = <SMI_L3_ID>; mediatek,smi = <&vpp_smi_common>; }; vdo1_rdma0: rdma@1c104000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c104000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; }; vdo1_rdma1: rdma@1c105000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c105000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; }; vdo1_rdma2: rdma@1c106000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c106000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; }; vdo1_rdma3: rdma@1c107000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c107000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; }; vdo1_rdma4: rdma@1c108000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c108000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; }; vdo1_rdma5: rdma@1c109000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c109000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; }; vdo1_rdma6: rdma@1c10a000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c10a000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; }; vdo1_rdma7: rdma@1c10b000 { compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; reg = <0 0x1c10b000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; #dma-cells = <1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; }; merge1: merge@1c10c000 { compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; reg = <0 0x1c10c000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; clock-names = "merge", "merge_async"; interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; mediatek,merge-mute; }; merge2: merge@1c10d000 { compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; reg = <0 0x1c10d000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; clock-names = "merge", "merge_async"; interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; mediatek,merge-mute; }; merge3: merge@1c10e000 { compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; reg = <0 0x1c10e000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; clock-names = "merge", "merge_async"; interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; mediatek,merge-mute; }; merge4: merge@1c10f000 { compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; reg = <0 0x1c10f000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; clock-names = "merge", "merge_async"; interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; mediatek,merge-mute; }; merge5: merge@1c110000 { compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; reg = <0 0x1c110000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; clock-names = "merge", "merge_async"; interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; mediatek,merge-fifo-en; }; dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8188-dp-intf"; reg = <0 0x1c113000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_DPINTF>, <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>, <&apmixedsys CLK_APMIXED_TVDPLL2>; clock-names = "pixel", "engine", "pll"; interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; status = "disabled"; }; ethdr0: ethdr@1c114000 { compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr"; reg = <0 0x1c114000 0 0x1000>, <0 0x1c115000 0 0x1000>, <0 0x1c117000 0 0x1000>, <0 0x1c119000 0 0x1000>, <0 0x1c11a000 0 0x1000>, <0 0x1c11b000 0 0x1000>, <0 0x1c11c000 0 0x1000>; reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", "vdo_be", "adl_ds"; clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, <&vdosys1 CLK_VDO1_HDR_VDO_BE>, <&vdosys1 CLK_VDO1_26M_SLOW>, <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, <&topckgen CLK_TOP_ETHDR>; clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; }; padding0: padding@1c11d000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c11d000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; }; padding1: padding@1c11e000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c11e000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING1>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; }; padding2: padding@1c11f000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c11f000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING2>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; }; padding3: padding@1c120000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c120000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING3>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; }; padding4: padding@1c121000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c121000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING4>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; }; padding5: padding@1c122000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c122000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING5>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; }; padding6: padding@1c123000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c123000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING6>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; }; padding7: padding@1c124000 { compatible = "mediatek,mt8188-disp-padding"; reg = <0 0x1c124000 0 0x1000>; clocks = <&vdosys1 CLK_VDO1_PADDING7>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; }; edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8188-edp-tx"; reg = <0 0x1c500000 0 0x8000>; interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; nvmem-cells = <&dp_calib_data>; nvmem-cell-names = "dp_calibration_data"; power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>; max-linkrate-mhz = <8100>; status = "disabled"; }; dp_tx: dp-tx@1c600000 { compatible = "mediatek,mt8188-dp-tx"; reg = <0 0x1c600000 0 0x8000>; interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; nvmem-cells = <&dp_calib_data>; nvmem-cell-names = "dp_calibration_data"; power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>; max-linkrate-mhz = <5400>; status = "disabled"; }; }; }; |