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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2019 MediaTek Inc. * Copyright (c) 2019 BayLibre, SAS. * Author: Fabien Parent <fparent@baylibre.com> */ #include <dt-bindings/clock/mt8516-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/phy/phy.h> #include "mt8516-pinfunc.h" / { compatible = "mediatek,mt8516"; interrupt-parent = <&sysirq>; #address-cells = <2>; #size-cells = <2>; cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-598000000 { opp-hz = /bits/ 64 <598000000>; opp-microvolt = <1150000>; }; opp-747500000 { opp-hz = /bits/ 64 <747500000>; opp-microvolt = <1150000>; }; opp-1040000000 { opp-hz = /bits/ 64 <1040000000>; opp-microvolt = <1200000>; }; opp-1196000000 { opp-hz = /bits/ 64 <1196000000>; opp-microvolt = <1250000>; }; opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; opp-microvolt = <1300000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x0>; enable-method = "psci"; cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; clocks = <&infracfg CLK_IFR_MUX1_SEL>, <&topckgen CLK_TOP_MAINPLL_D2>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x1>; enable-method = "psci"; cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; clocks = <&infracfg CLK_IFR_MUX1_SEL>, <&topckgen CLK_TOP_MAINPLL_D2>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x2>; enable-method = "psci"; cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; clocks = <&infracfg CLK_IFR_MUX1_SEL>, <&topckgen CLK_TOP_MAINPLL_D2>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0x3>; enable-method = "psci"; cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; clocks = <&infracfg CLK_IFR_MUX1_SEL>, <&topckgen CLK_TOP_MAINPLL_D2>; clock-names = "cpu", "intermediate", "armpll"; operating-points-v2 = <&cluster0_opp>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; entry-latency-us = <600>; exit-latency-us = <600>; min-residency-us = <1200>; arm,psci-suspend-param = <0x0010000>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; entry-latency-us = <800>; exit-latency-us = <1000>; min-residency-us = <2000>; arm,psci-suspend-param = <0x2010000>; }; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; clk26m: clk26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; clk32k: clk32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; clock-output-names = "clk32k"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ bl31_secmon_reserved: secmon@43000000 { no-map; reg = <0 0x43000000 0 0x30000>; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; pmu { compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges; topckgen: topckgen@10000000 { compatible = "mediatek,mt8516-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; }; infracfg: infracfg@10001000 { compatible = "mediatek,mt8516-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; }; pericfg: pericfg@10003050 { compatible = "mediatek,mt8516-pericfg", "syscon"; reg = <0 0x10003050 0 0x1000>; }; apmixedsys: apmixedsys@10018000 { compatible = "mediatek,mt8516-apmixedsys", "syscon"; reg = <0 0x10018000 0 0x710>; #clock-cells = <1>; }; watchdog@10007000 { compatible = "mediatek,mt8516-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x1000>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; #reset-cells = <1>; }; timer: timer@10008000 { compatible = "mediatek,mt8516-timer", "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_CLK26M_D2>, <&topckgen CLK_TOP_APXGPT>; clock-names = "clk13m", "bus"; }; keypad: keypad@10002000 { compatible = "mediatek,mt8516-keypad", "mediatek,mt6779-keypad"; reg = <0 0x10002000 0 0x1000>; wakeup-source; interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_FALLING>; clocks = <&clk26m>; clock-names = "kpd"; status = "disabled"; }; syscfg_pctl: syscfg-pctl@10005000 { compatible = "syscon"; reg = <0 0x10005000 0 0x1000>; }; pio: pinctrl@1000b000 { compatible = "mediatek,mt8516-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; }; efuse: efuse@10009000 { compatible = "mediatek,mt8516-efuse", "mediatek,efuse"; reg = <0 0x10009000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; }; pwrap: pwrap@1000f000 { compatible = "mediatek,mt8516-pwrap"; reg = <0 0x1000f000 0 0x1000>; reg-names = "pwrap"; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, <&topckgen CLK_TOP_PMICWRAP_AP>; clock-names = "spi", "wrap"; }; sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x10200620 0 0x20>; }; gic: interrupt-controller@10310000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x10310000 0 0x1000>, <0 0x1032f000 0 0x2000>, <0 0x10340000 0 0x2000>, <0 0x10360000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; apdma: dma-controller@11000480 { compatible = "mediatek,mt8516-uart-dma", "mediatek,mt6577-uart-dma"; reg = <0 0x11000480 0 0x80>, <0 0x11000500 0 0x80>, <0 0x11000580 0 0x80>, <0 0x11000600 0 0x80>, <0 0x11000980 0 0x80>, <0 0x11000a00 0 0x80>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>; dma-requests = <6>; clocks = <&topckgen CLK_TOP_APDMA>; clock-names = "apdma"; #dma-cells = <1>; }; uart0: serial@11005000 { compatible = "mediatek,mt8516-uart", "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_UART0_SEL>, <&topckgen CLK_TOP_UART0>; clock-names = "baud", "bus"; dmas = <&apdma 0 &apdma 1>; dma-names = "tx", "rx"; status = "disabled"; }; uart1: serial@11006000 { compatible = "mediatek,mt8516-uart", "mediatek,mt6577-uart"; reg = <0 0x11006000 0 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_UART1_SEL>, <&topckgen CLK_TOP_UART1>; clock-names = "baud", "bus"; dmas = <&apdma 2 &apdma 3>; dma-names = "tx", "rx"; status = "disabled"; }; uart2: serial@11007000 { compatible = "mediatek,mt8516-uart", "mediatek,mt6577-uart"; reg = <0 0x11007000 0 0x1000>; interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_UART2_SEL>, <&topckgen CLK_TOP_UART2>; clock-names = "baud", "bus"; dmas = <&apdma 4 &apdma 5>; dma-names = "tx", "rx"; status = "disabled"; }; i2c0: i2c@11009000 { compatible = "mediatek,mt8516-i2c", "mediatek,mt2712-i2c"; reg = <0 0x11009000 0 0x90>, <0 0x11000180 0 0x80>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; clock-div = <2>; clocks = <&topckgen CLK_TOP_I2C0>, <&topckgen CLK_TOP_APDMA>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c1: i2c@1100a000 { compatible = "mediatek,mt8516-i2c", "mediatek,mt2712-i2c"; reg = <0 0x1100a000 0 0x90>, <0 0x11000200 0 0x80>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; clock-div = <2>; clocks = <&topckgen CLK_TOP_I2C1>, <&topckgen CLK_TOP_APDMA>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@1100b000 { compatible = "mediatek,mt8516-i2c", "mediatek,mt2712-i2c"; reg = <0 0x1100b000 0 0x90>, <0 0x11000280 0 0x80>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; clock-div = <2>; clocks = <&topckgen CLK_TOP_I2C2>, <&topckgen CLK_TOP_APDMA>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; spi: spi@1100c000 { compatible = "mediatek,mt8516-spi", "mediatek,mt2712-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x1100c000 0 0x1000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, <&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SPI>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; mmc0: mmc@11120000 { compatible = "mediatek,mt8516-mmc"; reg = <0 0x11120000 0 0x1000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_MSDC0>, <&topckgen CLK_TOP_AHB_INFRA_SEL>, <&topckgen CLK_TOP_MSDC0_INFRA>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; mmc1: mmc@11130000 { compatible = "mediatek,mt8516-mmc"; reg = <0 0x11130000 0 0x1000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_MSDC1>, <&topckgen CLK_TOP_AHB_INFRA_SEL>, <&topckgen CLK_TOP_MSDC1_INFRA>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; mmc2: mmc@11170000 { compatible = "mediatek,mt8516-mmc"; reg = <0 0x11170000 0 0x1000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_MSDC2>, <&topckgen CLK_TOP_RG_MSDC2>, <&topckgen CLK_TOP_MSDC2_INFRA>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; ethernet: ethernet@11180000 { compatible = "mediatek,mt8516-eth"; reg = <0 0x11180000 0 0x1000>; mediatek,pericfg = <&pericfg>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_RG_ETH>, <&topckgen CLK_TOP_66M_ETH>, <&topckgen CLK_TOP_133M_ETH>; clock-names = "core", "reg", "trans"; status = "disabled"; }; rng: rng@1020c000 { compatible = "mediatek,mt8516-rng", "mediatek,mt7623-rng"; reg = <0 0x1020c000 0 0x100>; clocks = <&topckgen CLK_TOP_TRNG>; clock-names = "rng"; }; pwm: pwm@11008000 { compatible = "mediatek,mt8516-pwm"; reg = <0 0x11008000 0 0x1000>; #pwm-cells = <2>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; clocks = <&topckgen CLK_TOP_PWM>, <&topckgen CLK_TOP_PWM_B>, <&topckgen CLK_TOP_PWM1_FB>, <&topckgen CLK_TOP_PWM2_FB>, <&topckgen CLK_TOP_PWM3_FB>, <&topckgen CLK_TOP_PWM4_FB>, <&topckgen CLK_TOP_PWM5_FB>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5"; }; usb0: usb@11100000 { compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; reg = <0 0x11100000 0 0x1000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "mc"; phys = <&usb0_port PHY_TYPE_USB2>; clocks = <&topckgen CLK_TOP_USB>, <&topckgen CLK_TOP_USBIF>, <&topckgen CLK_TOP_USB_1P>; clock-names = "main","mcu","univpll"; status = "disabled"; }; usb1: usb@11190000 { compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; reg = <0 0x11190000 0 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "mc"; phys = <&usb1_port PHY_TYPE_USB2>; clocks = <&topckgen CLK_TOP_USB>, <&topckgen CLK_TOP_USBIF>, <&topckgen CLK_TOP_USB_1P>; clock-names = "main","mcu","univpll"; dr_mode = "host"; status = "disabled"; }; usb_phy: t-phy@11110000 { compatible = "mediatek,mt8516-tphy", "mediatek,generic-tphy-v1"; reg = <0 0x11110000 0 0x800>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; usb0_port: usb-phy@11110800 { reg = <0 0x11110800 0 0x100>; clocks = <&topckgen CLK_TOP_USB_PHY48M>; clock-names = "ref"; #phy-cells = <1>; }; usb1_port: usb-phy@11110900 { reg = <0 0x11110900 0 0x100>; clocks = <&topckgen CLK_TOP_USB_PHY48M>; clock-names = "ref"; #phy-cells = <1>; }; }; auxadc: adc@11003000 { compatible = "mediatek,mt8516-auxadc", "mediatek,mt8173-auxadc"; reg = <0 0x11003000 0 0x1000>; clocks = <&topckgen CLK_TOP_AUX_ADC>; clock-names = "main"; #io-channel-cells = <1>; status = "disabled"; }; }; }; |