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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * IPQ9574 RDP433 board device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> #include "ipq9574-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; }; &pcie1_phy { status = "okay"; }; &pcie1 { pinctrl-0 = <&pcie1_default>; pinctrl-names = "default"; perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; status = "okay"; }; &pcie2_phy { status = "okay"; }; &pcie2 { pinctrl-0 = <&pcie2_default>; pinctrl-names = "default"; perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; status = "okay"; }; &pcie3_phy { status = "okay"; }; &pcie3 { pinctrl-0 = <&pcie3_default>; pinctrl-names = "default"; perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; status = "okay"; }; &tlmm { pcie1_default: pcie1-default-state { clkreq-n-pins { pins = "gpio25"; function = "pcie1_clk"; drive-strength = <6>; bias-pull-up; }; perst-n-pins { pins = "gpio26"; function = "gpio"; drive-strength = <8>; bias-pull-down; output-low; }; wake-n-pins { pins = "gpio27"; function = "pcie1_wake"; drive-strength = <6>; bias-pull-up; }; }; pcie2_default: pcie2-default-state { clkreq-n-pins { pins = "gpio28"; function = "pcie2_clk"; drive-strength = <6>; bias-pull-up; }; perst-n-pins { pins = "gpio29"; function = "gpio"; drive-strength = <8>; bias-pull-down; output-low; }; wake-n-pins { pins = "gpio30"; function = "pcie2_wake"; drive-strength = <6>; bias-pull-up; }; }; pcie3_default: pcie3-default-state { clkreq-n-pins { pins = "gpio31"; function = "pcie3_clk"; drive-strength = <6>; bias-pull-up; }; perst-n-pins { pins = "gpio32"; function = "gpio"; drive-strength = <8>; bias-pull-up; output-low; }; wake-n-pins { pins = "gpio33"; function = "pcie3_wake"; drive-strength = <6>; bias-pull-up; }; }; }; |