Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 | // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) /* * Copyright (C) STMicroelectronics 2025 - All Rights Reserved * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. */ #include <dt-bindings/clock/st,stm32mp25-rcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/regulator/st,stm32mp25-regulator.h> #include <dt-bindings/reset/st,stm32mp25-rcc.h> / { #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a35"; reg = <0>; device_type = "cpu"; enable-method = "psci"; power-domains = <&cpu0_pd>; power-domain-names = "psci"; }; }; arm-pmu { compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>; interrupt-parent = <&intc>; }; arm_wdt: watchdog { compatible = "arm,smc-wdt"; arm,smc-id = <0xb200005a>; status = "disabled"; }; clk_dsi_txbyte: clock-0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; clk_rcbsec: clk-64000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <64000000>; }; firmware { optee: optee { compatible = "linaro,optee-tz"; method = "smc"; interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; scmi { compatible = "linaro,scmi-optee"; #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; }; scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; }; scmi_voltd: protocol@17 { reg = <0x17>; scmi_regu: regulators { #address-cells = <1>; #size-cells = <0>; scmi_vddio1: regulator@0 { reg = <VOLTD_SCMI_VDDIO1>; regulator-name = "vddio1"; }; scmi_vddio2: regulator@1 { reg = <VOLTD_SCMI_VDDIO2>; regulator-name = "vddio2"; }; scmi_vddio3: regulator@2 { reg = <VOLTD_SCMI_VDDIO3>; regulator-name = "vddio3"; }; scmi_vddio4: regulator@3 { reg = <VOLTD_SCMI_VDDIO4>; regulator-name = "vddio4"; }; scmi_vdd33ucpd: regulator@5 { reg = <VOLTD_SCMI_UCPD>; regulator-name = "vdd33ucpd"; }; scmi_vdda18adc: regulator@7 { reg = <VOLTD_SCMI_ADC>; regulator-name = "vdda18adc"; }; }; }; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; cpu0_pd: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; }; cluster_pd: power-domain-cluster { #power-domain-cells = <0>; power-domains = <&ret_pd>; }; ret_pd: power-domain-retention { #power-domain-cells = <0>; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&intc>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; always-on; }; soc@0 { compatible = "simple-bus"; ranges = <0x0 0x0 0x0 0x80000000>; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; hpdma: dma-controller@40400000 { compatible = "st,stm32mp25-dma3"; reg = <0x40400000 0x1000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scmi_clk CK_SCMI_HPDMA1>; #dma-cells = <3>; }; hpdma2: dma-controller@40410000 { compatible = "st,stm32mp25-dma3"; reg = <0x40410000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scmi_clk CK_SCMI_HPDMA2>; #dma-cells = <3>; }; hpdma3: dma-controller@40420000 { compatible = "st,stm32mp25-dma3"; reg = <0x40420000 0x1000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scmi_clk CK_SCMI_HPDMA3>; #dma-cells = <3>; }; rifsc: bus@42080000 { compatible = "st,stm32mp25-rifsc", "simple-bus"; reg = <0x42080000 0x1000>; ranges; #address-cells = <1>; #size-cells = <1>; #access-controller-cells = <1>; i2s2: audio-controller@400b0000 { compatible = "st,stm32mp25-i2s"; reg = <0x400b0000 0x400>; #sound-dai-cells = <0>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; clock-names = "pclk", "i2sclk"; resets = <&rcc SPI2_R>; dmas = <&hpdma 51 0x43 0x12>, <&hpdma 52 0x43 0x21>; dma-names = "rx", "tx"; access-controllers = <&rifsc 23>; status = "disabled"; }; spi2: spi@400b0000 { compatible = "st,stm32mp25-spi"; reg = <0x400b0000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_SPI2>; resets = <&rcc SPI2_R>; dmas = <&hpdma 51 0x20 0x3012>, <&hpdma 52 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 23>; power-domains = <&cluster_pd>; status = "disabled"; }; i2s3: audio-controller@400c0000 { compatible = "st,stm32mp25-i2s"; reg = <0x400c0000 0x400>; #sound-dai-cells = <0>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; clock-names = "pclk", "i2sclk"; resets = <&rcc SPI3_R>; dmas = <&hpdma 53 0x43 0x12>, <&hpdma 54 0x43 0x21>; dma-names = "rx", "tx"; access-controllers = <&rifsc 24>; status = "disabled"; }; spi3: spi@400c0000 { compatible = "st,stm32mp25-spi"; reg = <0x400c0000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_SPI3>; resets = <&rcc SPI3_R>; dmas = <&hpdma 53 0x20 0x3012>, <&hpdma 54 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 24>; power-domains = <&cluster_pd>; status = "disabled"; }; spdifrx: audio-controller@400d0000 { compatible = "st,stm32h7-spdifrx"; reg = <0x400d0000 0x400>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SPDIFRX>; clock-names = "kclk"; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; dmas = <&hpdma 71 0x43 0x212>, <&hpdma 72 0x43 0x212>; dma-names = "rx", "rx-ctrl"; access-controllers = <&rifsc 30>; status = "disabled"; }; usart2: serial@400e0000 { compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_USART2>; dmas = <&hpdma 11 0x20 0x10012>, <&hpdma 12 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 32>; status = "disabled"; }; usart3: serial@400f0000 { compatible = "st,stm32h7-uart"; reg = <0x400f0000 0x400>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_USART3>; dmas = <&hpdma 13 0x20 0x10012>, <&hpdma 14 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 33>; status = "disabled"; }; uart4: serial@40100000 { compatible = "st,stm32h7-uart"; reg = <0x40100000 0x400>; interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_UART4>; dmas = <&hpdma 15 0x20 0x10012>, <&hpdma 16 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 34>; status = "disabled"; }; uart5: serial@40110000 { compatible = "st,stm32h7-uart"; reg = <0x40110000 0x400>; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_UART5>; dmas = <&hpdma 17 0x20 0x10012>, <&hpdma 18 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 35>; status = "disabled"; }; i2c1: i2c@40120000 { compatible = "st,stm32mp25-i2c"; reg = <0x40120000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C1>; resets = <&rcc I2C1_R>; dmas = <&hpdma 27 0x20 0x3012>, <&hpdma 28 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; power-domains = <&cluster_pd>; i2c-analog-filter; status = "disabled"; }; i2c2: i2c@40130000 { compatible = "st,stm32mp25-i2c"; reg = <0x40130000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C2>; resets = <&rcc I2C2_R>; dmas = <&hpdma 30 0x20 0x3012>, <&hpdma 31 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; power-domains = <&cluster_pd>; i2c-analog-filter; status = "disabled"; }; i2c7: i2c@40180000 { compatible = "st,stm32mp25-i2c"; reg = <0x40180000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C7>; resets = <&rcc I2C7_R>; dmas = <&hpdma 45 0x20 0x3012>, <&hpdma 46 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; power-domains = <&cluster_pd>; i2c-analog-filter; status = "disabled"; }; usart6: serial@40220000 { compatible = "st,stm32h7-uart"; reg = <0x40220000 0x400>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_USART6>; dmas = <&hpdma 19 0x20 0x10012>, <&hpdma 20 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 36>; status = "disabled"; }; i2s1: audio-controller@40230000 { compatible = "st,stm32mp25-i2s"; reg = <0x40230000 0x400>; #sound-dai-cells = <0>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; clock-names = "pclk", "i2sclk"; resets = <&rcc SPI1_R>; dmas = <&hpdma 49 0x43 0x12>, <&hpdma 50 0x43 0x21>; dma-names = "rx", "tx"; access-controllers = <&rifsc 22>; status = "disabled"; }; spi1: spi@40230000 { compatible = "st,stm32mp25-spi"; reg = <0x40230000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_SPI1>; resets = <&rcc SPI1_R>; dmas = <&hpdma 49 0x20 0x3012>, <&hpdma 50 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 22>; power-domains = <&cluster_pd>; status = "disabled"; }; spi4: spi@40240000 { compatible = "st,stm32mp25-spi"; reg = <0x40240000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_SPI4>; resets = <&rcc SPI4_R>; dmas = <&hpdma 55 0x20 0x3012>, <&hpdma 56 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 25>; power-domains = <&cluster_pd>; status = "disabled"; }; spi5: spi@40280000 { compatible = "st,stm32mp25-spi"; reg = <0x40280000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_SPI5>; resets = <&rcc SPI5_R>; dmas = <&hpdma 57 0x20 0x3012>, <&hpdma 58 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 26>; power-domains = <&cluster_pd>; status = "disabled"; }; sai1: sai@40290000 { compatible = "st,stm32mp25-sai"; reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; ranges = <0 0x40290000 0x400>; #address-cells = <1>; #size-cells = <1>; clocks = <&rcc CK_BUS_SAI1>; clock-names = "pclk"; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; resets = <&rcc SAI1_R>; access-controllers = <&rifsc 49>; status = "disabled"; sai1a: audio-controller@40290004 { compatible = "st,stm32-sai-sub-a"; reg = <0x4 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI1>; clock-names = "sai_ck"; dmas = <&hpdma 73 0x43 0x21>; status = "disabled"; }; sai1b: audio-controller@40290024 { compatible = "st,stm32-sai-sub-b"; reg = <0x24 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI1>; clock-names = "sai_ck"; dmas = <&hpdma 74 0x43 0x12>; status = "disabled"; }; }; sai2: sai@402a0000 { compatible = "st,stm32mp25-sai"; reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; ranges = <0 0x402a0000 0x400>; #address-cells = <1>; #size-cells = <1>; clocks = <&rcc CK_BUS_SAI2>; clock-names = "pclk"; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; resets = <&rcc SAI2_R>; access-controllers = <&rifsc 50>; status = "disabled"; sai2a: audio-controller@402a0004 { compatible = "st,stm32-sai-sub-a"; reg = <0x4 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI2>; clock-names = "sai_ck"; dmas = <&hpdma 75 0x43 0x21>; status = "disabled"; }; sai2b: audio-controller@402a0024 { compatible = "st,stm32-sai-sub-b"; reg = <0x24 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI2>; clock-names = "sai_ck"; dmas = <&hpdma 76 0x43 0x12>; status = "disabled"; }; }; sai3: sai@402b0000 { compatible = "st,stm32mp25-sai"; reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; ranges = <0 0x402b0000 0x400>; #address-cells = <1>; #size-cells = <1>; clocks = <&rcc CK_BUS_SAI3>; clock-names = "pclk"; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; resets = <&rcc SAI3_R>; access-controllers = <&rifsc 51>; status = "disabled"; sai3a: audio-controller@402b0004 { compatible = "st,stm32-sai-sub-a"; reg = <0x4 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI3>; clock-names = "sai_ck"; dmas = <&hpdma 77 0x43 0x21>; status = "disabled"; }; sai3b: audio-controller@502b0024 { compatible = "st,stm32-sai-sub-b"; reg = <0x24 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI3>; clock-names = "sai_ck"; dmas = <&hpdma 78 0x43 0x12>; status = "disabled"; }; }; usart1: serial@40330000 { compatible = "st,stm32h7-uart"; reg = <0x40330000 0x400>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_USART1>; dmas = <&hpdma 9 0x20 0x10012>, <&hpdma 10 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 31>; status = "disabled"; }; sai4: sai@40340000 { compatible = "st,stm32mp25-sai"; reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; ranges = <0 0x40340000 0x400>; #address-cells = <1>; #size-cells = <1>; clocks = <&rcc CK_BUS_SAI4>; clock-names = "pclk"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; resets = <&rcc SAI4_R>; access-controllers = <&rifsc 52>; status = "disabled"; sai4a: audio-controller@40340004 { compatible = "st,stm32-sai-sub-a"; reg = <0x4 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI4>; clock-names = "sai_ck"; dmas = <&hpdma 79 0x63 0x21>; status = "disabled"; }; sai4b: audio-controller@40340024 { compatible = "st,stm32-sai-sub-b"; reg = <0x24 0x20>; #sound-dai-cells = <0>; clocks = <&rcc CK_KER_SAI4>; clock-names = "sai_ck"; dmas = <&hpdma 80 0x43 0x12>; status = "disabled"; }; }; uart7: serial@40370000 { compatible = "st,stm32h7-uart"; reg = <0x40370000 0x400>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_UART7>; dmas = <&hpdma 21 0x20 0x10012>, <&hpdma 22 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 37>; status = "disabled"; }; rng: rng@42020000 { compatible = "st,stm32mp25-rng"; reg = <0x42020000 0x400>; clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; clock-names = "core", "bus"; resets = <&rcc RNG_R>; access-controllers = <&rifsc 92>; status = "disabled"; }; spi8: spi@46020000 { compatible = "st,stm32mp25-spi"; reg = <0x46020000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_SPI8>; resets = <&rcc SPI8_R>; dmas = <&hpdma 171 0x20 0x3012>, <&hpdma 172 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 29>; status = "disabled"; }; i2c8: i2c@46040000 { compatible = "st,stm32mp25-i2c"; reg = <0x46040000 0x400>; #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C8>; resets = <&rcc I2C8_R>; dmas = <&hpdma 168 0x20 0x3012>, <&hpdma 169 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; power-domains = <&cluster_pd>; i2c-analog-filter; status = "disabled"; }; csi: csi@48020000 { compatible = "st,stm32mp25-csi"; reg = <0x48020000 0x2000>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; resets = <&rcc CSI_R>; clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, <&rcc CK_KER_CSIPHY>; clock-names = "pclk", "txesc", "csi2phy"; access-controllers = <&rifsc 86>; power-domains = <&cluster_pd>; status = "disabled"; }; dcmipp: dcmipp@48030000 { compatible = "st,stm32mp25-dcmipp"; reg = <0x48030000 0x1000>; interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; resets = <&rcc DCMIPP_R>; clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; clock-names = "kclk", "mclk"; access-controllers = <&rifsc 87>; power-domains = <&cluster_pd>; status = "disabled"; }; sdmmc1: mmc@48220000 { compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; reg = <0x48220000 0x400>, <0x44230400 0x8>; arm,primecell-periphid = <0x00353180>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_SDMMC1 >; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; access-controllers = <&rifsc 76>; status = "disabled"; }; ethernet1: ethernet@482c0000 { compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg = <0x482c0000 0x4000>; reg-names = "stmmaceth"; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", "ptp_ref", "ethstp", "eth-ck"; clocks = <&rcc CK_ETH1_MAC>, <&rcc CK_ETH1_TX>, <&rcc CK_ETH1_RX>, <&rcc CK_KER_ETH1PTP>, <&rcc CK_ETH1_STP>, <&rcc CK_KER_ETH1>; snps,axi-config = <&stmmac_axi_config_1>; snps,mixed-burst; snps,mtl-rx-config = <&mtl_rx_setup_1>; snps,mtl-tx-config = <&mtl_tx_setup_1>; snps,pbl = <2>; snps,tso; st,syscon = <&syscfg 0x3000>; access-controllers = <&rifsc 60>; status = "disabled"; mtl_rx_setup_1: rx-queues-config { snps,rx-queues-to-use = <2>; queue0 {}; queue1 {}; }; mtl_tx_setup_1: tx-queues-config { snps,tx-queues-to-use = <4>; queue0 {}; queue1 {}; queue2 {}; queue3 {}; }; stmmac_axi_config_1: stmmac-axi-config { snps,blen = <0 0 0 0 16 8 4>; snps,rd_osr_lmt = <0x7>; snps,wr_osr_lmt = <0x7>; }; }; }; bsec: efuse@44000000 { compatible = "st,stm32mp25-bsec"; reg = <0x44000000 0x1000>; #address-cells = <1>; #size-cells = <1>; part-number-otp@24 { reg = <0x24 0x4>; }; package-otp@1e8 { reg = <0x1e8 0x1>; bits = <0 3>; }; }; rcc: clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; #clock-cells = <1>; #reset-cells = <1>; clocks = <&scmi_clk CK_SCMI_HSE>, <&scmi_clk CK_SCMI_HSI>, <&scmi_clk CK_SCMI_MSI>, <&scmi_clk CK_SCMI_LSE>, <&scmi_clk CK_SCMI_LSI>, <&scmi_clk CK_SCMI_HSE_DIV2>, <&scmi_clk CK_SCMI_ICN_HS_MCU>, <&scmi_clk CK_SCMI_ICN_LS_MCU>, <&scmi_clk CK_SCMI_ICN_SDMMC>, <&scmi_clk CK_SCMI_ICN_DDR>, <&scmi_clk CK_SCMI_ICN_DISPLAY>, <&scmi_clk CK_SCMI_ICN_HSL>, <&scmi_clk CK_SCMI_ICN_NIC>, <&scmi_clk CK_SCMI_ICN_VID>, <&scmi_clk CK_SCMI_FLEXGEN_07>, <&scmi_clk CK_SCMI_FLEXGEN_08>, <&scmi_clk CK_SCMI_FLEXGEN_09>, <&scmi_clk CK_SCMI_FLEXGEN_10>, <&scmi_clk CK_SCMI_FLEXGEN_11>, <&scmi_clk CK_SCMI_FLEXGEN_12>, <&scmi_clk CK_SCMI_FLEXGEN_13>, <&scmi_clk CK_SCMI_FLEXGEN_14>, <&scmi_clk CK_SCMI_FLEXGEN_15>, <&scmi_clk CK_SCMI_FLEXGEN_16>, <&scmi_clk CK_SCMI_FLEXGEN_17>, <&scmi_clk CK_SCMI_FLEXGEN_18>, <&scmi_clk CK_SCMI_FLEXGEN_19>, <&scmi_clk CK_SCMI_FLEXGEN_20>, <&scmi_clk CK_SCMI_FLEXGEN_21>, <&scmi_clk CK_SCMI_FLEXGEN_22>, <&scmi_clk CK_SCMI_FLEXGEN_23>, <&scmi_clk CK_SCMI_FLEXGEN_24>, <&scmi_clk CK_SCMI_FLEXGEN_25>, <&scmi_clk CK_SCMI_FLEXGEN_26>, <&scmi_clk CK_SCMI_FLEXGEN_27>, <&scmi_clk CK_SCMI_FLEXGEN_28>, <&scmi_clk CK_SCMI_FLEXGEN_29>, <&scmi_clk CK_SCMI_FLEXGEN_30>, <&scmi_clk CK_SCMI_FLEXGEN_31>, <&scmi_clk CK_SCMI_FLEXGEN_32>, <&scmi_clk CK_SCMI_FLEXGEN_33>, <&scmi_clk CK_SCMI_FLEXGEN_34>, <&scmi_clk CK_SCMI_FLEXGEN_35>, <&scmi_clk CK_SCMI_FLEXGEN_36>, <&scmi_clk CK_SCMI_FLEXGEN_37>, <&scmi_clk CK_SCMI_FLEXGEN_38>, <&scmi_clk CK_SCMI_FLEXGEN_39>, <&scmi_clk CK_SCMI_FLEXGEN_40>, <&scmi_clk CK_SCMI_FLEXGEN_41>, <&scmi_clk CK_SCMI_FLEXGEN_42>, <&scmi_clk CK_SCMI_FLEXGEN_43>, <&scmi_clk CK_SCMI_FLEXGEN_44>, <&scmi_clk CK_SCMI_FLEXGEN_45>, <&scmi_clk CK_SCMI_FLEXGEN_46>, <&scmi_clk CK_SCMI_FLEXGEN_47>, <&scmi_clk CK_SCMI_FLEXGEN_48>, <&scmi_clk CK_SCMI_FLEXGEN_49>, <&scmi_clk CK_SCMI_FLEXGEN_50>, <&scmi_clk CK_SCMI_FLEXGEN_51>, <&scmi_clk CK_SCMI_FLEXGEN_52>, <&scmi_clk CK_SCMI_FLEXGEN_53>, <&scmi_clk CK_SCMI_FLEXGEN_54>, <&scmi_clk CK_SCMI_FLEXGEN_55>, <&scmi_clk CK_SCMI_FLEXGEN_56>, <&scmi_clk CK_SCMI_FLEXGEN_57>, <&scmi_clk CK_SCMI_FLEXGEN_58>, <&scmi_clk CK_SCMI_FLEXGEN_59>, <&scmi_clk CK_SCMI_FLEXGEN_60>, <&scmi_clk CK_SCMI_FLEXGEN_61>, <&scmi_clk CK_SCMI_FLEXGEN_62>, <&scmi_clk CK_SCMI_FLEXGEN_63>, <&scmi_clk CK_SCMI_ICN_APB1>, <&scmi_clk CK_SCMI_ICN_APB2>, <&scmi_clk CK_SCMI_ICN_APB3>, <&scmi_clk CK_SCMI_ICN_APB4>, <&scmi_clk CK_SCMI_ICN_APBDBG>, <&scmi_clk CK_SCMI_TIMG1>, <&scmi_clk CK_SCMI_TIMG2>, <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; access-controllers = <&rifsc 156>; }; exti1: interrupt-controller@44220000 { compatible = "st,stm32mp1-exti", "syscon"; reg = <0x44220000 0x400>; interrupt-controller; #interrupt-cells = <2>; interrupts-extended = <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, <0>, /* EXTI_20 */ <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <0>, <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <0>, /* EXTI_60 */ <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <0>, <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ <0>, <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, <0>, /* EXTI_80 */ <0>, <0>, <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; }; syscfg: syscon@44230000 { compatible = "st,stm32mp23-syscfg", "syscon"; reg = <0x44230000 0x10000>; }; pinctrl: pinctrl@44240000 { compatible = "st,stm32mp257-pinctrl"; ranges = <0 0x44240000 0xa0400>; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&exti1>; st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; gpioa: gpio@44240000 { reg = <0x0 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOA>; st,bank-name = "GPIOA"; status = "disabled"; }; gpiob: gpio@44250000 { reg = <0x10000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOB>; st,bank-name = "GPIOB"; status = "disabled"; }; gpioc: gpio@44260000 { reg = <0x20000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOC>; st,bank-name = "GPIOC"; status = "disabled"; }; gpiod: gpio@44270000 { reg = <0x30000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOD>; st,bank-name = "GPIOD"; status = "disabled"; }; gpioe: gpio@44280000 { reg = <0x40000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOE>; st,bank-name = "GPIOE"; status = "disabled"; }; gpiof: gpio@44290000 { reg = <0x50000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOF>; st,bank-name = "GPIOF"; status = "disabled"; }; gpiog: gpio@442a0000 { reg = <0x60000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOG>; st,bank-name = "GPIOG"; status = "disabled"; }; gpioh: gpio@442b0000 { reg = <0x70000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOH>; st,bank-name = "GPIOH"; status = "disabled"; }; gpioi: gpio@442c0000 { reg = <0x80000 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOI>; st,bank-name = "GPIOI"; status = "disabled"; }; }; rtc: rtc@46000000 { compatible = "st,stm32mp25-rtc"; reg = <0x46000000 0x400>; clocks = <&scmi_clk CK_SCMI_RTC>, <&scmi_clk CK_SCMI_RTCCK>; clock-names = "pclk", "rtc_ck"; interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; pinctrl_z: pinctrl@46200000 { compatible = "st,stm32mp257-z-pinctrl"; ranges = <0 0x46200000 0x400>; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&exti1>; st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; gpioz: gpio@46200000 { reg = <0 0x400>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; }; }; exti2: interrupt-controller@46230000 { compatible = "st,stm32mp1-exti", "syscon"; reg = <0x46230000 0x400>; interrupt-controller; #interrupt-cells = <2>; interrupts-extended = <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <0>, /* EXTI_20 */ <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <0>, <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, <0>, <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ <0>, <0>, <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <0>, <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, /* EXTI_60 */ <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, <0>, <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>, <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ }; intc: interrupt-controller@4ac10000 { compatible = "arm,gic-400"; reg = <0x4ac10000 0x1000>, <0x4ac20000 0x20000>, <0x4ac40000 0x20000>, <0x4ac60000 0x20000>; #interrupt-cells = <3>; interrupt-controller; }; }; }; |