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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 | /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ #ifndef _PFE_H_ #define _PFE_H_ #include <elf.h> #include <linux/bitops.h> #include "cbus.h" #define PFE_RESET_WA #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */ #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) #define CLASS_DMEM_SIZE 0x00002000 #define CLASS_IMEM_SIZE 0x00008000 #define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) /* Only valid for mem access register interface */ #define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) #define TMU_DMEM_SIZE 0x00000800 #define TMU_IMEM_SIZE 0x00002000 #define UTIL_DMEM_BASE_ADDR 0x00000000 #define UTIL_DMEM_SIZE 0x00002000 #define PE_LMEM_BASE_ADDR 0xc3010000 #define PE_LMEM_SIZE 0x8000 #define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE) #define DMEM_BASE_ADDR 0x00000000 #define DMEM_SIZE 0x2000 /* TMU has less... */ #define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE) #define PMEM_BASE_ADDR 0x00010000 #define PMEM_SIZE 0x8000 /* TMU has less... */ #define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE) /* Memory ranges check from PE point of view/memory map */ #define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\ (((unsigned long)(addr) +\ (len)) <= DMEM_END)) #define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\ (((unsigned long)(addr) +\ (len)) <= PMEM_END)) #define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\ ) && (((unsigned long)(addr)\ + (len)) <= PE_LMEM_END)) #define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\ (((unsigned long)(addr) + (len)) <=\ CBUS_VIRT_TO_PFE(LMEM_END))) #define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\ PFE_DDR_PHYS_BASE_ADDR) &&\ (((unsigned long)(addr) + (len)) <=\ PFE_DDR_PHYS_END)) /* Host View Address */ extern void *ddr_pfe_base_addr; /* PFE View Address */ /* DDR physical base address as seen by PE's. */ #define PFE_DDR_PHYS_BASE_ADDR 0x03800000 #define PFE_DDR_PHYS_SIZE 0xC000000 #define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE) /* CBUS physical base address as seen by PE's. */ #define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* Host<->PFE Mapping */ #define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p) + 0x80000000)) #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\ PFE_CBUS_PHYS_BASE_ADDR) #define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\ CBUS_BASE_ADDR) enum { CLASS0_ID = 0, CLASS1_ID, CLASS2_ID, CLASS3_ID, CLASS4_ID, CLASS5_ID, TMU0_ID, TMU1_ID, TMU2_ID, TMU3_ID, MAX_PE }; #define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\ | BIT(CLASS3_ID) | BIT(CLASS4_ID) |\ BIT(CLASS5_ID)) #define CLASS_MAX_ID CLASS5_ID #define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID)) #define TMU_MAX_ID TMU3_ID /* * PE information. * Structure containing PE's specific information. It is used to create * generic C functions common to all PEs. * Before using the library functions this structure needs to be * initialized with the different registers virtual addresses * (according to the ARM MMU mmaping). The default initialization supports a * virtual == physical mapping. * */ struct pe_info { u32 dmem_base_addr; /* PE's dmem base address */ u32 pmem_base_addr; /* PE's pmem base address */ u32 pmem_size; /* PE's pmem size */ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA * register address */ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR * register address */ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA * register address */ }; void pe_lmem_read(u32 *dst, u32 len, u32 offset); void pe_lmem_write(u32 *src, u32 len, u32 offset); u32 pe_pmem_read(int id, u32 addr, u8 size); void pe_dmem_write(int id, u32 val, u32 addr, u8 size); u32 pe_dmem_read(int id, u32 addr, u8 size); int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr); void pfe_lib_init(void); void bmu_init(void *base, struct bmu_cfg *cfg); void bmu_enable(void *base); void gpi_init(void *base, struct gpi_cfg *cfg); void gpi_enable(void *base); void gpi_disable(void *base); void class_init(struct class_cfg *cfg); void class_enable(void); void class_disable(void); void tmu_init(struct tmu_cfg *cfg); void tmu_enable(u32 pe_mask); void tmu_disable(u32 pe_mask); void hif_init(void); void hif_tx_enable(void); void hif_tx_disable(void); void hif_rx_enable(void); void hif_rx_disable(void); void hif_rx_desc_disable(void); #ifdef PFE_RESET_WA void pfe_command_stop(int argc, char *const argv[]); #else static void pfe_command_stop(int argc, char *const argv[]) {} #endif #endif /* _PFE_H_ */ |