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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 | #ifndef __S2MPS11__H__ #define __S2MPS11__H__ enum s2mps11_reg { S2MPS11_REG_ID = 0, S2MPS11_REG_INT1, S2MPS11_REG_INT2, S2MPS11_REG_INT3, S2MPS11_REG_INT1M, S2MPS11_REG_INT2M, S2MPS11_REG_INT3M, S2MPS11_REG_STATUS1, S2MPS11_REG_STATUS2, S2MPS11_REG_OFFSRC, S2MPS11_REG_PWRONSRC, S2MPS11_REG_RTC_CTRL, S2MPS11_REG_CTRL1, S2MPS11_REG_ETC_TEST, S2MPS11_REG_RSVD3, S2MPS11_REG_BU_CHG, S2MPS11_REG_RAMP, S2MPS11_REG_RAMP_BUCK, S2MPS11_REG_LDO1_8, S2MPS11_REG_LDO9_16, S2MPS11_REG_LDO17_24, S2MPS11_REG_LDO25_32, S2MPS11_REG_LDO33_38, S2MPS11_REG_LDO1_8_OVC, S2MPS11_REG_LDO9_16_OVC, S2MPS11_REG_LDO17_24_OVC, S2MPS11_REG_LDO25_32_OVC, S2MPS11_REG_LDO33_38_OVC, S2MPS11_REG_RESERVED1, S2MPS11_REG_RESERVED2, S2MPS11_REG_RESERVED3, S2MPS11_REG_RESERVED4, S2MPS11_REG_RESERVED5, S2MPS11_REG_RESERVED6, S2MPS11_REG_RESERVED7, S2MPS11_REG_RESERVED8, S2MPS11_REG_WDRSTEN_CTRL, S2MPS11_REG_B1CTRL1, S2MPS11_REG_B1CTRL2, S2MPS11_REG_B2CTRL1, S2MPS11_REG_B2CTRL2, S2MPS11_REG_B3CTRL1, S2MPS11_REG_B3CTRL2, S2MPS11_REG_B4CTRL1, S2MPS11_REG_B4CTRL2, S2MPS11_REG_B5CTRL1, S2MPS11_REG_BUCK5_SW, S2MPS11_REG_B5CTRL2, S2MPS11_REG_B5CTRL3, S2MPS11_REG_B5CTRL4, S2MPS11_REG_B5CTRL5, S2MPS11_REG_B6CTRL1, S2MPS11_REG_B6CTRL2, S2MPS11_REG_B7CTRL1, S2MPS11_REG_B7CTRL2, S2MPS11_REG_B8CTRL1, S2MPS11_REG_B8CTRL2, S2MPS11_REG_B9CTRL1, S2MPS11_REG_B9CTRL2, S2MPS11_REG_B10CTRL1, S2MPS11_REG_B10CTRL2, S2MPS11_REG_L1CTRL, S2MPS11_REG_L2CTRL, S2MPS11_REG_L3CTRL, S2MPS11_REG_L4CTRL, S2MPS11_REG_L5CTRL, S2MPS11_REG_L6CTRL, S2MPS11_REG_L7CTRL, S2MPS11_REG_L8CTRL, S2MPS11_REG_L9CTRL, S2MPS11_REG_L10CTRL, S2MPS11_REG_L11CTRL, S2MPS11_REG_L12CTRL, S2MPS11_REG_L13CTRL, S2MPS11_REG_L14CTRL, S2MPS11_REG_L15CTRL, S2MPS11_REG_L16CTRL, S2MPS11_REG_L17CTRL, S2MPS11_REG_L18CTRL, S2MPS11_REG_L19CTRL, S2MPS11_REG_L20CTRL, S2MPS11_REG_L21CTRL, S2MPS11_REG_L22CTRL, S2MPS11_REG_L23CTRL, S2MPS11_REG_L24CTRL, S2MPS11_REG_L25CTRL, S2MPS11_REG_L26CTRL, S2MPS11_REG_L27CTRL, S2MPS11_REG_L28CTRL, S2MPS11_REG_L29CTRL, S2MPS11_REG_L30CTRL, S2MPS11_REG_L31CTRL, S2MPS11_REG_L32CTRL, S2MPS11_REG_L33CTRL, S2MPS11_REG_L34CTRL, S2MPS11_REG_L35CTRL, S2MPS11_REG_L36CTRL, S2MPS11_REG_L37CTRL, S2MPS11_REG_L38CTRL, S2MPS11_REG_COUNT, }; #define S2MPS11_LDO26_ENABLE 0xec /* Driver name */ #define S2MPS11_BUCK_DRIVER "s2mps11_buck" #define S2MPS11_OF_BUCK_PREFIX "BUCK" #define S2MPS11_LDO_DRIVER "s2mps11_ldo" #define S2MPS11_OF_LDO_PREFIX "LDO" /* BUCK */ #define S2MPS11_BUCK_VOLT_MASK 0xff #define S2MPS11_BUCK9_VOLT_MASK 0x1f #define S2MPS11_BUCK_LSTEP 6250 #define S2MPS11_BUCK_HSTEP 12500 #define S2MPS11_BUCK9_STEP 25000 #define S2MPS11_BUCK_UV_MIN 600000 #define S2MPS11_BUCK_UV_HMIN 750000 #define S2MPS11_BUCK9_UV_MIN 1400000 #define S2MPS11_BUCK_VOLT_MAX_HEX 0xA0 #define S2MPS11_BUCK5_VOLT_MAX_HEX 0xDF #define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX 0xDC #define S2MPS11_BUCK9_VOLT_MAX_HEX 0x5F #define S2MPS11_BUCK_MODE_SHIFT 6 #define S2MPS11_BUCK_MODE_MASK (0x3) #define S2MPS11_BUCK_MODE_OFF (0x0 << 6) #define S2MPS11_BUCK_MODE_STANDBY (0x1 << 6) #define S2MPS11_BUCK_MODE_ON (0x3 << 6) /* LDO */ #define S2MPS11_LDO_VOLT_MASK 0x3F #define S2MPS11_LDO_VOLT_MAX_HEX 0x3F #define S2MPS11_LDO_STEP 25000 #define S2MPS11_LDO_UV_MIN 800000 #define S2MPS11_LDO_MODE_MASK 0x3 #define S2MPS11_LDO_MODE_SHIFT 6 #define S2MPS11_LDO_MODE_OFF (0x0 << 6) #define S2MPS11_LDO_MODE_STANDBY (0x1 << 6) #define S2MPS11_LDO_MODE_STANDBY_LPM (0x2 << 6) #define S2MPS11_LDO_MODE_ON (0x3 << 6) enum s2mpu05_reg { S2MPU05_REG_ID, S2MPU05_REG_INT1, S2MPU05_REG_INT2, S2MPU05_REG_INT3, S2MPU05_REG_INT1M, S2MPU05_REG_INT2M, S2MPU05_REG_INT3M, S2MPU05_REG_ST1, S2MPU05_REG_ST2, S2MPU05_REG_PWRONSRC, S2MPU05_REG_OFFSRC, S2MPU05_REG_BU_CHG, S2MPU05_REG_RTC_BUF, S2MPU05_REG_CTRL1, S2MPU05_REG_CTRL2, S2MPU05_REG_ETC_TEST, S2MPU05_REG_OTP_ADRL, S2MPU05_REG_OTP_ADRH, S2MPU05_REG_OTP_DATA, S2MPU05_REG_MON1SEL, S2MPU05_REG_MON2SEL, S2MPU05_REG_CTRL3, S2MPU05_REG_ETC_OTP, S2MPU05_REG_UVLO, S2MPU05_REG_TIME_CTRL1, S2MPU05_REG_TIME_CTRL2, S2MPU05_REG_B1CTRL1, S2MPU05_REG_B1CTRL2, S2MPU05_REG_B2CTRL1, S2MPU05_REG_B2CTRL2, S2MPU05_REG_B2CTRL3, S2MPU05_REG_B2CTRL4, S2MPU05_REG_B3CTRL1, S2MPU05_REG_B3CTRL2, S2MPU05_REG_B3CTRL3, S2MPU05_REG_B4CTRL1, S2MPU05_REG_B4CTRL2, S2MPU05_REG_B5CTRL1, S2MPU05_REG_B5CTRL2, S2MPU05_REG_BUCK_RAMP, S2MPU05_REG_LDO_DVS1, S2MPU05_REG_LDO_DVS9, S2MPU05_REG_LDO_DVS10, S2MPU05_REG_L1CTRL, S2MPU05_REG_L2CTRL, S2MPU05_REG_L3CTRL, S2MPU05_REG_L4CTRL, S2MPU05_REG_L5CTRL, S2MPU05_REG_L6CTRL, S2MPU05_REG_L7CTRL, S2MPU05_REG_L8CTRL, S2MPU05_REG_L9CTRL1, S2MPU05_REG_L9CTRL2, S2MPU05_REG_L10CTRL, S2MPU05_REG_L11CTRL1, S2MPU05_REG_L11CTRL2, S2MPU05_REG_L12CTRL, S2MPU05_REG_L13CTRL, S2MPU05_REG_L14CTRL, S2MPU05_REG_L15CTRL, S2MPU05_REG_L16CTRL, S2MPU05_REG_L17CTRL1, S2MPU05_REG_L17CTRL2, S2MPU05_REG_L18CTRL1, S2MPU05_REG_L18CTRL2, S2MPU05_REG_L19CTRL, S2MPU05_REG_L20CTRL, S2MPU05_REG_L21CTRL, S2MPU05_REG_L22CTRL, S2MPU05_REG_L23CTRL, S2MPU05_REG_L24CTRL, S2MPU05_REG_L25CTRL, S2MPU05_REG_L26CTRL, S2MPU05_REG_L27CTRL, S2MPU05_REG_L28CTRL, S2MPU05_REG_L29CTRL, S2MPU05_REG_L30CTRL, S2MPU05_REG_L31CTRL, S2MPU05_REG_L32CTRL, S2MPU05_REG_L33CTRL, S2MPU05_REG_L34CTRL, S2MPU05_REG_L35CTRL, S2MPU05_REG_LDO_DSCH1, S2MPU05_REG_LDO_DSCH2, S2MPU05_REG_LDO_DSCH3, S2MPU05_REG_LDO_DSCH4, S2MPU05_REG_LDO_DSCH5, S2MPU05_REG_LDO_CTRL1, S2MPU05_REG_LDO_CTRL2, S2MPU05_REG_TCXO_CTRL, S2MPU05_REG_SELMIF, S2MPU05_REG_COUNT, }; #define S2MPU05_OF_BUCK_PREFIX "buck" #define S2MPU05_OF_LDO_PREFIX "ldo" /* BUCK */ #define S2MPU05_BUCK_MIN1 400000 #define S2MPU05_BUCK_MIN2 600000 #define S2MPU05_BUCK_STEP1 6250 #define S2MPU05_BUCK_STEP2 12500 /* LDO */ #define S2MPU05_LDO_MIN1 800000 #define S2MPU05_LDO_MIN2 1800000 #define S2MPU05_LDO_MIN3 400000 #define S2MPU05_LDO_STEP1 12500 #define S2MPU05_LDO_STEP2 25000 struct sec_regulator_desc { /* regulator mode control */ unsigned int mode_reg; unsigned int mode_mask; /* regulator voltage control */ unsigned int volt_reg; unsigned int volt_mask; unsigned int volt_min; unsigned int volt_step; unsigned int volt_max_hex; }; enum { OP_OFF = 0, OP_LPM, OP_STANDBY, OP_STANDBY_LPM, OP_ON, }; enum { VARIANT_NONE, VARIANT_S2MPS11, VARIANT_S2MPU05, }; #endif |