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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 | // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ #include <config.h> #include <irq_func.h> /* * CPU test * Logic instructions: andi., andis. * * The test contains a pre-built table of instructions, operands and * expected results. For each table entry, the test will cyclically use * different sets of operand registers and result registers. */ #include <post.h> #include "cpu_asm.h" #if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); static struct cpu_post_andi_s { ulong cmd; ulong op1; ushort op2; ulong res; } cpu_post_andi_table[] = { { OP_ANDI_, 0x80008000, 0xffff, 0x00008000 }, { OP_ANDIS_, 0x80008000, 0xffff, 0x80000000 }, }; static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table); int cpu_post_test_andi (void) { int ret = 0; unsigned int i, reg; int flag = disable_interrupts(); for (i = 0; i < cpu_post_andi_size && ret == 0; i++) { struct cpu_post_andi_s *test = cpu_post_andi_table + i; for (reg = 0; reg < 32 && ret == 0; reg++) { unsigned int reg0 = (reg + 0) % 32; unsigned int reg1 = (reg + 1) % 32; unsigned int stk = reg < 16 ? 31 : 15; unsigned long codecr[] = { ASM_STW(stk, 1, -4), ASM_ADDI(stk, 1, -16), ASM_STW(3, stk, 8), ASM_STW(reg0, stk, 4), ASM_STW(reg1, stk, 0), ASM_LWZ(reg0, stk, 8), ASM_11IX(test->cmd, reg1, reg0, test->op2), ASM_STW(reg1, stk, 8), ASM_LWZ(reg1, stk, 0), ASM_LWZ(reg0, stk, 4), ASM_LWZ(3, stk, 8), ASM_ADDI(1, stk, 16), ASM_LWZ(stk, 1, -4), ASM_BLR, }; ulong res; ulong cr; cpu_post_exec_21 (codecr, & cr, & res, test->op1); ret = res == test->res && (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; if (ret != 0) { post_log ("Error at andi test %d !\n", i); } } } if (flag) enable_interrupts(); return ret; } #endif |