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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 | /* * (C) Copyright 2002 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <common.h> #include <ppc4xx.h> #include <asm/processor.h> #include <pci.h> #ifdef CONFIG_SDRAM_BANK0 #define MAGIC0 0x00000000 #define MAGIC1 0x11111111 #define MAGIC2 0x22222222 #define MAGIC3 0x33333333 #define MAGIC4 0x44444444 #define ADDR_ZERO 0x00000000 #define ADDR_400 0x00000400 #define ADDR_08MB 0x00800000 #define ADDR_16MB 0x01000000 #define ADDR_32MB 0x02000000 #define ADDR_64MB 0x04000000 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) /*----------------------------------------------------------------------- */ void sdram_init(void) { ulong speed; ulong sdtr1; ulong rtr; /* * Determine SDRAM speed */ speed = get_bus_freq(0); /* parameter not used on ppc4xx */ /* * Support for 100MHz and 133MHz SDRAM */ if (speed > 100000000) { /* * 133 MHz SDRAM */ sdtr1 = 0x01074015; rtr = 0x07f00000; } else { /* * default: 100 MHz SDRAM */ sdtr1 = 0x0086400d; rtr = 0x05f00000; } /* * Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4) */ mtsdram0(mem_mb0cf, 0x00084001); mtsdram0(mem_sdtr1, sdtr1); mtsdram0(mem_rtr, rtr); /* * Wait for 200us */ udelay(200); /* * Set memory controller options reg, MCOPT1. * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ mtsdram0(mem_mcopt1, 0x80800000); /* * Wait for 10ms */ udelay(10000); /* * Test if 64 MByte are equipped (mirror test) */ *(volatile ulong *)ADDR_ZERO = MAGIC0; *(volatile ulong *)ADDR_08MB = MAGIC1; *(volatile ulong *)ADDR_16MB = MAGIC2; *(volatile ulong *)ADDR_32MB = MAGIC3; if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && (*(volatile ulong *)ADDR_08MB == MAGIC1) && (*(volatile ulong *)ADDR_16MB == MAGIC2)) { /* * OK, 64MB detected -> all done */ return; } /* * Now test for 32 MByte... */ /* * Disable memory controller. */ mtsdram0(mem_mcopt1, 0x00000000); /* * Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4) */ mtsdram0(mem_mb0cf, 0x00062001); /* * Set memory controller options reg, MCOPT1. * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ mtsdram0(mem_mcopt1, 0x80800000); /* * Wait for 10ms */ udelay(10000); /* * Test if 32 MByte are equipped (mirror test) */ *(volatile ulong *)ADDR_ZERO = MAGIC0; *(volatile ulong *)ADDR_400 = MAGIC1; *(volatile ulong *)ADDR_08MB = MAGIC2; *(volatile ulong *)ADDR_16MB = MAGIC3; if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) && (*(volatile ulong *)ADDR_400 == MAGIC1) && (*(volatile ulong *)ADDR_08MB == MAGIC2)) { /* * OK, 32MB detected -> all done */ return; } /* * Setup for 16 MByte... */ /* * Disable memory controller. */ mtsdram0(mem_mcopt1, 0x00000000); /* * Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4) */ mtsdram0(mem_mb0cf, 0x00046001); /* * Set memory controller options reg, MCOPT1. * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ mtsdram0(mem_mcopt1, 0x80800000); /* * Wait for 10ms */ udelay(10000); } #endif /* CONFIG_SDRAM_BANK0 */ |