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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 | /* * MPC8260 Internal Memory Map * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) * * The Internal Memory Map of the 8260. I don't know how generic * this will be, as I don't have any knowledge of the subsequent * parts at this time. I copied this from the 8xx_immap.h. */ #ifndef __IMMAP_82XX__ #define __IMMAP_82XX__ /* System configuration registers. */ typedef struct sys_conf { uint sc_siumcr; uint sc_sypcr; char res1[6]; ushort sc_swsr; char res2[20]; uint sc_bcr; u_char sc_ppc_acr; char res3[3]; uint sc_ppc_alrh; uint sc_ppc_alrl; u_char sc_lcl_acr; char res4[3]; uint sc_lcl_alrh; uint sc_lcl_alrl; uint sc_tescr1; uint sc_tescr2; uint sc_ltescr1; uint sc_ltescr2; uint sc_pdtea; u_char sc_pdtem; char res5[3]; uint sc_ldtea; u_char sc_ldtem; char res6[163]; } sysconf8260_t; /* Memory controller registers. */ typedef struct mem_ctlr { uint memc_br0; uint memc_or0; uint memc_br1; uint memc_or1; uint memc_br2; uint memc_or2; uint memc_br3; uint memc_or3; uint memc_br4; uint memc_or4; uint memc_br5; uint memc_or5; uint memc_br6; uint memc_or6; uint memc_br7; uint memc_or7; uint memc_br8; uint memc_or8; uint memc_br9; uint memc_or9; uint memc_br10; uint memc_or10; uint memc_br11; uint memc_or11; char res1[8]; uint memc_mar; char res2[4]; uint memc_mamr; uint memc_mbmr; uint memc_mcmr; char res3[8]; ushort memc_mptpr; char res4[2]; uint memc_mdr; char res5[4]; uint memc_psdmr; uint memc_lsdmr; u_char memc_purt; char res6[3]; u_char memc_psrt; char res7[3]; u_char memc_lurt; char res8[3]; u_char memc_lsrt; char res9[3]; uint memc_immr; char res10[84]; } memctl8260_t; /* System Integration Timers. */ typedef struct sys_int_timers { char res1[32]; ushort sit_tmcntsc; char res2[2]; uint sit_tmcnt; char res3[4]; uint sit_tmcntal; char res4[16]; ushort sit_piscr; char res5[2]; uint sit_pitc; uint sit_pitr; char res6[94]; char res7[2390]; } sit8260_t; #define PISCR_PIRQ_MASK ((ushort)0xff00) #define PISCR_PS ((ushort)0x0080) #define PISCR_PIE ((ushort)0x0004) #define PISCR_PTF ((ushort)0x0002) #define PISCR_PTE ((ushort)0x0001) /* Interrupt Controller. */ typedef struct interrupt_controller { ushort ic_sicr; char res1[2]; uint ic_sivec; uint ic_sipnrh; uint ic_sipnrl; uint ic_siprr; uint ic_scprrh; uint ic_scprrl; uint ic_simrh; uint ic_simrl; uint ic_siexr; char res2[88]; } intctl8260_t; /* Clocks and Reset. */ typedef struct clk_and_reset { uint car_sccr; char res1[4]; uint car_scmr; char res2[4]; uint car_rsr; uint car_rmr; char res[104]; } car8260_t; /* Input/Output Port control/status registers. * Names consistent with processor manual, although they are different * from the original 8xx names....... */ typedef struct io_port { uint iop_pdira; uint iop_ppara; uint iop_psora; uint iop_podra; uint iop_pdata; char res1[12]; uint iop_pdirb; uint iop_pparb; uint iop_psorb; uint iop_podrb; uint iop_pdatb; char res2[12]; uint iop_pdirc; uint iop_pparc; uint iop_psorc; uint iop_podrc; uint iop_pdatc; char res3[12]; uint iop_pdird; uint iop_ppard; uint iop_psord; uint iop_podrd; uint iop_pdatd; char res4[12]; } iop8260_t; /* Communication Processor Module Timers */ typedef struct cpm_timers { u_char cpmt_tgcr1; char res1[3]; u_char cpmt_tgcr2; char res2[11]; ushort cpmt_tmr1; ushort cpmt_tmr2; ushort cpmt_trr1; ushort cpmt_trr2; ushort cpmt_tcr1; ushort cpmt_tcr2; ushort cpmt_tcn1; ushort cpmt_tcn2; ushort cpmt_tmr3; ushort cpmt_tmr4; ushort cpmt_trr3; ushort cpmt_trr4; ushort cpmt_tcr3; ushort cpmt_tcr4; ushort cpmt_tcn3; ushort cpmt_tcn4; ushort cpmt_ter1; ushort cpmt_ter2; ushort cpmt_ter3; ushort cpmt_ter4; char res3[584]; } cpmtimer8260_t; /* DMA control/status registers. */ typedef struct sdma_csr { char res0[24]; u_char sdma_sdsr; char res1[3]; u_char sdma_sdmr; char res2[3]; u_char sdma_idsr1; char res3[3]; u_char sdma_idmr1; char res4[3]; u_char sdma_idsr2; char res5[3]; u_char sdma_idmr2; char res6[3]; u_char sdma_idsr3; char res7[3]; u_char sdma_idmr3; char res8[3]; u_char sdma_idsr4; char res9[3]; u_char sdma_idmr4; char res10[707]; } sdma8260_t; /* Fast controllers */ typedef struct fcc { uint fcc_gfmr; uint fcc_fpsmr; ushort fcc_ftodr; char res1[2]; ushort fcc_fdsr; char res2[2]; ushort fcc_fcce; char res3[2]; ushort fcc_fccm; char res4[2]; u_char fcc_fccs; char res5[3]; u_char fcc_ftirr_phy[4]; } fcc_t; /* I2C */ typedef struct i2c { u_char i2c_i2mod; char res1[3]; u_char i2c_i2add; char res2[3]; u_char i2c_i2brg; char res3[3]; u_char i2c_i2com; char res4[3]; u_char i2c_i2cer; char res5[3]; u_char i2c_i2cmr; char res6[331]; } i2c8260_t; typedef struct scc { /* Serial communication channels */ uint scc_gsmrl; uint scc_gsmrh; ushort scc_psmr; char res1[2]; ushort scc_todr; ushort scc_dsr; ushort scc_scce; char res2[2]; ushort scc_sccm; char res3; u_char scc_sccs; char res4[8]; } scc_t; typedef struct smc { /* Serial management channels */ char res1[2]; ushort smc_smcmr; char res2[2]; u_char smc_smce; char res3[3]; u_char smc_smcm; char res4[5]; } smc_t; /* Serial Peripheral Interface. */ typedef struct im_spi { ushort spi_spmode; char res1[4]; u_char spi_spie; char res2[3]; u_char spi_spim; char res3[2]; u_char spi_spcom; char res4[82]; } im_spi_t; /* CPM Mux. */ typedef struct cpmux { u_char cmx_si1cr; char res1; u_char cmx_si2cr; char res2; uint cmx_fcr; uint cmx_scr; u_char cmx_smr; char res3; ushort cmx_uar; char res4[16]; } cpmux_t; /* SIRAM control */ typedef struct siram { ushort si_amr; ushort si_bmr; ushort si_cmr; ushort si_dmr; u_char si_gmr; char res1; u_char si_cmdr; char res2; u_char si_str; char res3; ushort si_rsr; } siramctl_t; typedef struct mcc { ushort mcc_mcce; char res1[2]; ushort mcc_mccm; char res2[2]; u_char mcc_mccf; char res3[7]; } mcc_t; typedef struct comm_proc { uint cp_cpcr; uint cp_rccr; char res1[14]; ushort cp_rter; char res2[2]; ushort cp_rtmr; ushort cp_rtscr; char res3[2]; uint cp_rtsr; char res4[12]; } cpm8260_t; /* ...and the whole thing wrapped up.... */ typedef struct immap { /* Some references are into the unique and known dpram spaces, * others are from the generic base. */ #define im_dprambase im_dpram1 u_char im_dpram1[16*1024]; char res1[16*1024]; u_char im_dpram2[4*1024]; char res2[8*1024]; u_char im_dpram3[4*1024]; char res3[16*1024]; sysconf8260_t im_siu_conf; /* SIU Configuration */ memctl8260_t im_memctl; /* Memory Controller */ sit8260_t im_sit; /* System Integration Timers */ intctl8260_t im_intctl; /* Interrupt Controller */ car8260_t im_clkrst; /* Clocks and reset */ iop8260_t im_ioport; /* IO Port control/status */ cpmtimer8260_t im_cpmtimer; /* CPM timers */ sdma8260_t im_sdma; /* SDMA control/status */ fcc_t im_fcc[3]; /* Three FCCs */ char res4[159]; /* First set of baud rate generators. */ char res4a[496]; uint im_brgc5; uint im_brgc6; uint im_brgc7; uint im_brgc8; char res5[608]; i2c8260_t im_i2c; /* I2C control/status */ cpm8260_t im_cpm; /* Communication processor */ /* Second set of baud rate generators. */ uint im_brgc1; uint im_brgc2; uint im_brgc3; uint im_brgc4; scc_t im_scc[4]; /* Four SCCs */ smc_t im_smc[2]; /* Couple of SMCs */ im_spi_t im_spi; /* A SPI */ cpmux_t im_cpmux; /* CPM clock route mux */ siramctl_t im_siramctl1; /* First SI RAM Control */ mcc_t im_mcc1; /* First MCC */ siramctl_t im_siramctl2; /* Second SI RAM Control */ mcc_t im_mcc2; /* Second MCC */ char res6[1184]; ushort im_si1txram[256]; char res7[512]; ushort im_si1rxram[256]; char res8[512]; ushort im_si2txram[256]; char res9[512]; ushort im_si2rxram[256]; char res10[512]; char res11[4096]; } immap_t; #endif /* __IMMAP_82XX__ */ |