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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 | # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # ifeq ($(ARCH),ppc) LOAD_ADDR = 0x40000 endif ifeq ($(ARCH),i386) LOAD_ADDR = 0x40000 endif ifeq ($(ARCH),arm) LOAD_ADDR = 0xc100000 endif ifeq ($(ARCH),mips) LOAD_ADDR = 0x80200000 -T mips.lds endif ifeq ($(ARCH),nios) LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds endif ifeq ($(ARCH),nios2) LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds endif ifeq ($(ARCH),m68k) LOAD_ADDR = 0x20000 -L $(clibdir) endif ifeq ($(ARCH),microblaze) LOAD_ADDR = 0x80F00000 endif ifeq ($(ARCH),blackfin) LOAD_ADDR = 0x1000 endif include $(TOPDIR)/config.mk SREC = hello_world.srec BIN = hello_world.bin hello_world ifeq ($(CPU),mpc8xx) SREC = test_burst.srec BIN = test_burst.bin test_burst endif ifeq ($(ARCH),i386) SREC += 82559_eeprom.srec BIN += 82559_eeprom.bin 82559_eeprom endif ifeq ($(ARCH),ppc) SREC += sched.srec BIN += sched.bin sched endif ifeq ($(ARCH),blackfin) SREC += smc91111_eeprom.srec BIN += smc91111_eeprom.bin smc91111_eeprom endif # The following example is pretty 8xx specific... ifeq ($(CPU),mpc8xx) SREC += timer.srec BIN += timer.bin timer endif # The following example is 8260 specific... ifeq ($(CPU),mpc8260) SREC += mem_to_mem_idma2intr.srec BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr endif # Demo for 52xx IRQs ifeq ($(CPU),mpc5xxx) SREC += interrupt.srec BIN += interrupt.bin interrupt endif # Utility for resetting i82559 EEPROM ifeq ($(BOARD),oxc) SREC += eepro100_eeprom.srec BIN += eepro100_eeprom.bin eepro100_eeprom endif ifeq ($(BIG_ENDIAN),y) EX_LDFLAGS += -EB endif COBJS := $(SREC:.srec=.o) LIB = $(obj)libstubs.a LIBAOBJS= ifeq ($(ARCH),ppc) LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o endif ifeq ($(CPU),mpc8xx) LIBAOBJS+= test_burst_lib.o endif LIBCOBJS= stubs.o LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS)) SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(if $(LIBAOBJS),$(LIBAOBJS:.o=.S)) OBJS := $(addprefix $(obj),$(COBJS)) BIN := $(addprefix $(obj),$(BIN)) SREC := $(addprefix $(obj),$(SREC)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) CPPFLAGS += -I.. all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) ######################################################################### $(LIB): $(obj).depend $(LIBOBJS) $(AR) $(ARFLAGS) $@ $(LIBOBJS) $(obj)%: $(obj)%.o $(LIB) $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ -o $@ -e $(notdir $(<:.o=)) $< $(LIB) \ -L$(gcclibdir) -lgcc $(obj)%.srec: $(obj)% $(OBJCOPY) -O srec $< $@ 2>/dev/null $(obj)%.bin: $(obj)% $(OBJCOPY) -O binary $< $@ 2>/dev/null ######################################################################### # defines $(obj).depend target include $(SRCTREE)/rules.mk sinclude $(obj).depend ######################################################################### |