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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 | // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * * MCF5282 additionals * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> * * MCF5275 additions * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) * * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. */ #include <init.h> #include <net.h> #include <vsprintf.h> #include <command.h> #include <asm/global_data.h> #include <asm/immap.h> #include <asm/io.h> #include <netdev.h> #include <linux/delay.h> #include "cpu.h" DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_M5208 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { rcm_t *rcm = (rcm_t *)(MMAP_RCM); udelay(1000); out_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; }; #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { char buf1[32], buf2[32]; printf("CPU: Freescale Coldfire MCF5208\n" " CPU CLK %s MHz BUS CLK %s MHz\n", strmhz(buf1, gd->cpu_clk), strmhz(buf2, gd->bus_clk)); return 0; }; #endif /* CONFIG_DISPLAY_CPUINFO */ #endif /* #ifdef CONFIG_M5208 */ #ifdef CONFIG_M5271 #if defined(CONFIG_DISPLAY_CPUINFO) /* * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to * determine which one we are running on, based on the Chip Identification * Register (CIR). */ int print_cpuinfo(void) { char buf[32]; unsigned short cir; /* Chip Identification Register */ unsigned short pin; /* Part identification number */ unsigned char prn; /* Part revision number */ char *cpu_model; cir = mbar_readShort(MCF_CCM_CIR); pin = cir >> MCF_CCM_CIR_PIN_LEN; prn = cir & MCF_CCM_CIR_PRN_MASK; switch (pin) { case MCF_CCM_CIR_PIN_MCF5270: cpu_model = "5270"; break; case MCF_CCM_CIR_PIN_MCF5271: cpu_model = "5271"; break; default: cpu_model = NULL; break; } if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", cpu_model, prn, strmhz(buf, CFG_SYS_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" " (PIN: 0x%x) rev. %hu, at %s MHz\n", pin, prn, strmhz(buf, CFG_SYS_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { /* Call the board specific reset actions first. */ if(board_reset) { board_reset(); } mbar_writeByte(MCF_RCM_RCR, MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); return 0; }; #endif #ifdef CONFIG_M5272 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { wdog_t *wdp = (wdog_t *) (MMAP_WDOG); out_be16(&wdp->wdog_wrrr, 0); udelay(1000); /* enable watchdog, set timeout to 0 and wait */ out_be16(&wdp->wdog_wrrr, 1); while (1) ; /* we don't return! */ return 0; }; #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); uchar msk; char *suf; puts("CPU: "); msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf; switch (msk) { case 0x2: suf = "1K75N"; break; case 0x4: suf = "3K75N"; break; default: suf = NULL; printf("Freescale MCF5272 (Mask:%01x)\n", msk); break; } if (suf) printf("Freescale MCF5272 %s\n", suf); return 0; }; #endif /* CONFIG_DISPLAY_CPUINFO */ #endif /* #ifdef CONFIG_M5272 */ #ifdef CONFIG_M5275 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { rcm_t *rcm = (rcm_t *)(MMAP_RCM); udelay(1000); out_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; }; #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { char buf[32]; printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", strmhz(buf, CFG_SYS_CLK)); return 0; }; #endif /* CONFIG_DISPLAY_CPUINFO */ #endif /* #ifdef CONFIG_M5275 */ #ifdef CONFIG_M5282 #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { unsigned char resetsource = MCFRESET_RSR; printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); printf("Reset:%s%s%s%s%s%s%s\n", (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", (resetsource & MCFRESET_RSR_EXT) ? " External" : "", (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { MCFRESET_RCR = MCFRESET_RCR_SOFTRST; return 0; }; #endif #ifdef CONFIG_M5249 #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { char buf[32]; printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_SYS_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { /* enable watchdog, set timeout to 0 and wait */ mbar_writeByte(MCFSIM_SYPCR, 0xc0); while (1) ; /* we don't return! */ return 0; }; #endif #ifdef CONFIG_M5253 #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { char buf[32]; unsigned char resetsource = mbar_readLong(SIM_RSR); printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", strmhz(buf, CFG_SYS_CLK)); if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { printf("Reset:%s%s\n", (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" : "", (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : ""); } return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { /* enable watchdog, set timeout to 0 and wait */ mbar_writeByte(SIM_SYPCR, 0xc0); while (1) ; /* we don't return! */ return 0; }; #endif #if defined(CONFIG_MCFFEC) /* Default initializations for MCFFEC controllers. To override, * create a board-specific function called: * int board_eth_init(struct bd_info *bis) */ int cpu_eth_init(struct bd_info *bis) { return mcffec_initialize(bis); } #endif |