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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017 Andes Technology Corporation * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ #include <cpu_func.h> #include <dm.h> #include <asm/insn-def.h> #include <linux/const.h> #include <linux/errno.h> #define CBO_INVAL(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(0)) #define CBO_CLEAN(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(1)) #define CBO_FLUSH(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(2)) enum { CBO_CLEAN, CBO_FLUSH, CBO_INVAL } riscv_cbo_ops; static int zicbom_block_size; extern unsigned int riscv_get_cbom_block_size(void); static inline void do_cbo_clean(unsigned long base) { asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) :: "r"(base) : "memory"); } static inline void do_cbo_flush(unsigned long base) { asm volatile ("add a0, %0, zero\n" CBO_FLUSH(%0) :: "r"(base) : "memory"); } static inline void do_cbo_inval(unsigned long base) { asm volatile ("add a0, %0, zero\n" CBO_INVAL(%0) :: "r"(base) : "memory"); } static void cbo_op(int op_type, unsigned long start, unsigned long end) { unsigned long op_size = end - start, size = 0; void (*fn)(unsigned long base); switch (op_type) { case CBO_CLEAN: fn = do_cbo_clean; break; case CBO_FLUSH: fn = do_cbo_flush; break; case CBO_INVAL: fn = do_cbo_inval; break; } start &= ~(UL(zicbom_block_size - 1)); while (size < op_size) { fn(start + size); size += zicbom_block_size; } } void cbo_flush(unsigned long start, unsigned long end) { if (zicbom_block_size) cbo_op(CBO_FLUSH, start, end); } void cbo_inval(unsigned long start, unsigned long end) { if (zicbom_block_size) cbo_op(CBO_INVAL, start, end); } void invalidate_icache_all(void) { asm volatile ("fence.i" ::: "memory"); } __weak void flush_dcache_all(void) { } __weak void flush_dcache_range(unsigned long start, unsigned long end) { cbo_flush(start, end); } __weak void invalidate_icache_range(unsigned long start, unsigned long end) { /* * RISC-V does not have an instruction for invalidating parts of the * instruction cache. Invalidate all of it instead. */ invalidate_icache_all(); } __weak void invalidate_dcache_range(unsigned long start, unsigned long end) { cbo_inval(start, end); } void cache_flush(void) { invalidate_icache_all(); flush_dcache_all(); } void flush_cache(unsigned long addr, unsigned long size) { invalidate_icache_range(addr, addr + size); flush_dcache_range(addr, addr + size); } __weak void icache_enable(void) { } __weak void icache_disable(void) { } __weak int icache_status(void) { return 0; } __weak void dcache_enable(void) { } __weak void dcache_disable(void) { } __weak int dcache_status(void) { return 0; } __weak void enable_caches(void) { zicbom_block_size = riscv_get_cbom_block_size(); if (!zicbom_block_size) log_debug("Zicbom not initialized.\n"); } int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) { return -ENOSYS; } |