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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 | // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Google, Inc * Written by Simon Glass <sjg@chromium.org> */ #include <config.h> / { binman { multiple-images; rom: rom { }; }; }; #ifdef CONFIG_ROM_SIZE &rom { filename = "u-boot.rom"; end-at-4gb; sort-by-offset; pad-byte = <0xff>; size = <CONFIG_ROM_SIZE>; #ifdef CONFIG_HAVE_INTEL_ME intel-descriptor { filename = CONFIG_FLASH_DESCRIPTOR_FILE; assume-size = <0x1000>; }; intel-me { filename = CONFIG_INTEL_ME_FILE; assume-size = <0x1ff000>; }; #endif #ifdef CONFIG_TPL #ifdef CONFIG_HAVE_MICROCODE u-boot-tpl-with-ucode-ptr { offset = <CONFIG_TPL_TEXT_BASE>; }; u-boot-tpl-dtb { }; #endif u-boot-spl { type = "u-boot-spl"; offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot { offset = <CONFIG_X86_OFFSET_U_BOOT>; }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-dtb-with-ucode2 { type = "u-boot-dtb-with-ucode"; }; u-boot { offset = <CONFIG_X86_OFFSET_U_BOOT>; }; #else # ifdef CONFIG_HAVE_MICROCODE /* If there is no SPL then we need to put microcode in U-Boot */ u-boot-with-ucode-ptr { offset = <CONFIG_X86_OFFSET_U_BOOT>; }; # else u-boot-nodtb { offset = <CONFIG_X86_OFFSET_U_BOOT>; }; # endif #endif #ifdef CONFIG_HAVE_MICROCODE u-boot-dtb-with-ucode { }; u-boot-ucode { align = <16>; }; #else u-boot-dtb { }; #endif fdtmap { }; #ifdef CONFIG_HAVE_X86_FIT intel-fit { }; intel-fit-ptr { }; #endif #ifdef CONFIG_HAVE_MRC intel-mrc { offset = <CFG_X86_MRC_ADDR>; assume-size = <0x2fc94>; }; #endif #ifdef CONFIG_FSP_VERSION1 intel-fsp { filename = CONFIG_FSP_FILE; offset = <CONFIG_FSP_ADDR>; }; #endif #ifdef CONFIG_FSP_VERSION2 intel-descriptor { filename = CONFIG_FLASH_DESCRIPTOR_FILE; assume-size = <4096>; }; intel-ifwi { filename = CONFIG_IFWI_INPUT_FILE; convert-fit; section { size = <0x8000>; ifwi-replace; ifwi-subpart = "IBBP"; ifwi-entry = "IBBL"; u-boot-tpl { }; x86-start16-tpl { offset = <0x7800>; }; x86-reset16-tpl { offset = <0x7ff0>; }; }; }; intel-fsp-m { filename = CONFIG_FSP_FILE_M; }; intel-fsp-s { filename = CONFIG_FSP_FILE_S; }; #endif private_files: private-files { type = "files"; pattern = "*.dat"; }; #ifdef CONFIG_HAVE_CMC intel-cmc { filename = CONFIG_CMC_FILE; offset = <CONFIG_CMC_ADDR>; }; #endif #ifdef CONFIG_HAVE_VGA_BIOS intel-vga { filename = CONFIG_VGA_BIOS_FILE; offset = <CONFIG_VGA_BIOS_ADDR>; assume-size = <0x10000>; }; #endif #ifdef CONFIG_HAVE_VBT intel-vbt { filename = CONFIG_VBT_FILE; offset = <CONFIG_VBT_ADDR>; }; #endif #ifdef CONFIG_HAVE_REFCODE intel-refcode { offset = <CFG_X86_REFCODE_ADDR>; }; #endif #ifdef CONFIG_TPL x86-start16-tpl { offset = <CONFIG_SYS_X86_START16>; }; x86-reset16-tpl { offset = <CONFIG_RESET_VEC_LOC>; }; #elif defined(CONFIG_SPL) x86-start16-spl { offset = <CONFIG_SYS_X86_START16>; }; x86-reset16-spl { offset = <CONFIG_RESET_VEC_LOC>; }; #else x86-start16 { offset = <CONFIG_SYS_X86_START16>; }; x86-reset16 { offset = <CONFIG_RESET_VEC_LOC>; }; #endif image-header { location = "end"; }; }; #endif |