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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 | /* SPDX-License-Identifier: GPL-2.0+ */ /* * Miscellaneous assembly functions. * * Copyright (C) 2001 - 2007 Tensilica Inc. * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. * * Chris Zankel <chris@zankel.net> */ #include <linux/linkage.h> #include <asm/asmmacro.h> #include <asm/cacheasm.h> /* * void __invalidate_icache_page(ulong start) */ ENTRY(__invalidate_icache_page) abi_entry ___invalidate_icache_page a2 a3 isync abi_ret ENDPROC(__invalidate_icache_page) /* * void __invalidate_dcache_page(ulong start) */ ENTRY(__invalidate_dcache_page) abi_entry ___invalidate_dcache_page a2 a3 dsync abi_ret ENDPROC(__invalidate_dcache_page) /* * void __flush_invalidate_dcache_page(ulong start) */ ENTRY(__flush_invalidate_dcache_page) abi_entry ___flush_invalidate_dcache_page a2 a3 dsync abi_ret ENDPROC(__flush_invalidate_dcache_page) /* * void __flush_dcache_page(ulong start) */ ENTRY(__flush_dcache_page) abi_entry ___flush_dcache_page a2 a3 dsync abi_ret ENDPROC(__flush_dcache_page) /* * void __invalidate_icache_range(ulong start, ulong size) */ ENTRY(__invalidate_icache_range) abi_entry ___invalidate_icache_range a2 a3 a4 isync abi_ret ENDPROC(__invalidate_icache_range) /* * void __flush_invalidate_dcache_range(ulong start, ulong size) */ ENTRY(__flush_invalidate_dcache_range) abi_entry ___flush_invalidate_dcache_range a2 a3 a4 dsync abi_ret ENDPROC(__flush_invalidate_dcache_range) /* * void _flush_dcache_range(ulong start, ulong size) */ ENTRY(__flush_dcache_range) abi_entry ___flush_dcache_range a2 a3 a4 dsync abi_ret ENDPROC(__flush_dcache_range) /* * void _invalidate_dcache_range(ulong start, ulong size) */ ENTRY(__invalidate_dcache_range) abi_entry ___invalidate_dcache_range a2 a3 a4 abi_ret ENDPROC(__invalidate_dcache_range) /* * void _invalidate_icache_all(void) */ ENTRY(__invalidate_icache_all) abi_entry ___invalidate_icache_all a2 a3 isync abi_ret ENDPROC(__invalidate_icache_all) /* * void _flush_invalidate_dcache_all(void) */ ENTRY(__flush_invalidate_dcache_all) abi_entry ___flush_invalidate_dcache_all a2 a3 dsync abi_ret ENDPROC(__flush_invalidate_dcache_all) /* * void _invalidate_dcache_all(void) */ ENTRY(__invalidate_dcache_all) abi_entry ___invalidate_dcache_all a2 a3 dsync abi_ret ENDPROC(__invalidate_dcache_all) |