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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 | // SPDX-License-Identifier: GPL-2.0+ #include <cpu_func.h> #include <hang.h> #include <init.h> #include <log.h> #include <spl.h> #include <asm/io.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/arch/clock.h> #include <asm/arch/imx8mm_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/arch/ddr.h> #include <asm/sections.h> #include <dm/uclass.h> #include <dm/device.h> #include <dm/uclass-internal.h> #include <dm/device-internal.h> #include <power/pmic.h> #include <power/bd71837.h> int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { case SD2_BOOT: case MMC2_BOOT: return BOOT_DEVICE_MMC1; case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC2; case USB_BOOT: return BOOT_DEVICE_BOARD; case QSPI_BOOT: return BOOT_DEVICE_NOR; default: return BOOT_DEVICE_NONE; } } static void spl_dram_init(void) { ddr_init(&dram_timing); } void spl_board_init(void) { arch_misc_init(); } #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { /* Just empty function now - can't decide what to choose */ debug("%s: %s\n", __func__, name); return 0; } #endif static int power_init_board(void) { struct udevice *dev; int ret; ret = pmic_get("pmic@4b", &dev); if (ret == -ENODEV) { puts("No pmic\n"); return 0; } if (ret != 0) return ret; /* decrease RESET key long push time from the default 10s to 10ms */ pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); /* unlock the PMIC regs */ pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); /* increase VDD_SOC to typical value 0.85v before first DRAM access */ pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); /* lock the PMIC regs */ pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); return 0; } void board_init_f(ulong dummy) { struct udevice *dev; int ret; arch_cpu_init(); timer_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); if (ret < 0) { printf("Failed to find clock node. Check device tree\n"); hang(); } preloader_console_init(); enable_tzc380(); power_init_board(); /* DDR initialization */ spl_dram_init(); board_init_r(NULL, 0); } |